code wiki / _hdl_build / _gpu_dxg_r5a_fence.nx
_gpu_dxg_r5a_fence.nx
buildroot/runtime/_hdl_build/_gpu_dxg_r5a_fence.nx
about
_gpu_dxg_r5a_fence.nx -- SOVEREIGN-GPU R5a-v2: prove the real 5080 EXECUTES a Nishi-emitted pushbuffer by
having a host/FIFO semaphore-release write to a MONITORED FENCE's GPU VA (whose CPU mirror reflects GPU-engine
signals -- R4g finding). This sidesteps EXISTINGHEAP CPU-coherency: the monitored-fence page is GPU-coherent by
design. If the fence CPU value becomes our payload, the GPU ran our sovereign commands.
chain -> context(R4a) -> paging queue(R4c) -> monitored fence(R4g: fence_cpu_va@union24, fence_gpu_va@union32)
-> pushbuffer alloc(R4d)+map(R4e)+resident(R4f) -> EMIT sem-release(value->fence_gpu_va) -> SUBMITCOMMAND
(command_buffer@0=pb_va, command_length@8=24, broadcast_context_count@0x18=1, broadcast_context[0]@0x1c=context)
-> poll fence_cpu_va for the payload. raw syscalls only. license_tier: ORIGINAL
dependencies 1 imports · 0 importers
imports: nx_syscalls.nx
imported by: nobody (leaf or entry point)
call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown
structs
| none |
consts
| 12 | const ENUM2_CODE: i64 = 0xC0104714 |
| 13 | const QAI_CODE: i64 = 0xC0184709 |
| 14 | const OAFL_CODE: i64 = 0xC00C4701 |
| 15 | const CDEV_CODE: i64 = 0xC0404702 |
| 16 | const CCV_CODE: i64 = 0xC0284704 |
| 17 | const CPQ_CODE: i64 = 0xC0204707 |
| 18 | const CSO_CODE: i64 = 0xC0604710 |
| 19 | const CALLOC_CODE: i64 = 0xC0484706 |
| 20 | const MAPVA_CODE: i64 = 0xC068470C |
| 21 | const MKRES_CODE: i64 = 0xC030470B |
| 22 | const SUBMIT_CODE: i64 = 0xC180470F |
functions
| 24 | func p(s: *u8) -> i64 { var nn: i64=0; while s[nn]!=(0 as u8){nn=nn+1} sys_write(1,s,nn); return 0 } |
| 25 | func n(v: i64) -> i64 { let bb: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m;sys_write(1,"-" as *u8,1)}; let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48;k=1}; while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1}; var i: i64=0; while i<k{bb[i]=t[k-1-i];i=i+1}; sys_write(1,bb,k); return 0 } |
| 26 | func x(v: i64) -> i64 { p("0x" as *u8); let bb:*u8=sys_mmap(20); var k:i64=0; var m:i64=v; if m==0{bb[0]=48;k=1}; while m>0{ let d:i64=m&15; if d<10{bb[k]=(48+d) as u8}else{bb[k]=(87+d) as u8}; m=(m>>4); k=k+1 } var i:i64=0; let o:*u8=sys_mmap(20); while i<k{o[i]=bb[k-1-i];i=i+1} sys_write(1,o,k); return 0 } |
| 27 | func rd32(buf: *u8, off: i64) -> i64 { return (buf[off] as i64)|((buf[off+1] as i64)<<8)|((buf[off+2] as i64)<<16)|((buf[off+3] as i64)<<24) } |
| 28 | func rd64(buf: *u8, off: i64) -> i64 { let q: *i64 = (buf as i64 + off) as *i64; return q[0] } |
| 29 | func setu32(buf: *u8, off: i64, val: i64) -> i64 { let w: *u8 = (buf as i64 + off) as *u8; w[0]=(val&0xff) as u8; w[1]=((val>>8)&0xff) as u8; w[2]=((val>>16)&0xff) as u8; w[3]=((val>>24)&0xff) as u8; return 0 } |
| 30 | func setu64(buf: *u8, off: i64, val: i64) -> i64 { let q: *i64 = (buf as i64 + off) as *i64; q[0]=val; return 0 } |
| 32 | func query_type(fd: i64, handle: i64, qtype: i64, psize: i64, outv: *i64) -> i64 |
| 40 | func open_from_luid(fd: i64, luid_lo: i64, luid_hi: i64, outh: *i64) -> i64 |
| 45 | func create_device(fd: i64, adapter: i64, outd: *i64) -> i64 |
| 50 | func create_ctx(fd: i64, device: i64, outc: *i64) -> i64 |
| 55 | func create_pq(fd: i64, device: i64, outpq: *i64) -> i64 |
| 61 | func create_mf(fd: i64, device: i64, outso: *i64, outcva: *i64, outgva: *i64) -> i64 |
| 66 | func alloc_eh(fd: i64, device: i64, sysmem: *u8, outh: *i64) -> i64 |
| 76 | func map_va(fd: i64, pq: i64, alloc: i64, outva: *i64) -> i64 |
| 82 | func makeresident(fd: i64, pq: i64, alloc_handle: i64) -> i64 |
| 90 | func main() -> i64 |