_gpu_dxg_r5a_fence.nx source

1// _gpu_dxg_r5a_fence.nx -- SOVEREIGN-GPU R5a-v2: prove the real 5080 EXECUTES a Nishi-emitted pushbuffer by 2// having a host/FIFO semaphore-release write to a MONITORED FENCE's GPU VA (whose CPU mirror reflects GPU-engine 3// signals -- R4g finding). This sidesteps EXISTINGHEAP CPU-coherency: the monitored-fence page is GPU-coherent by 4// design. If the fence CPU value becomes our payload, the GPU ran our sovereign commands. 5// 6// chain -> context(R4a) -> paging queue(R4c) -> monitored fence(R4g: fence_cpu_va@union24, fence_gpu_va@union32) 7// -> pushbuffer alloc(R4d)+map(R4e)+resident(R4f) -> EMIT sem-release(value->fence_gpu_va) -> SUBMITCOMMAND 8// (command_buffer@0=pb_va, command_length@8=24, broadcast_context_count@0x18=1, broadcast_context[0]@0x1c=context) 9// -> poll fence_cpu_va for the payload. raw syscalls only. license_tier: ORIGINAL 10import "nx_syscalls.nx" 11 12const ENUM2_CODE: i64 = 0xC0104714 13const QAI_CODE: i64 = 0xC0184709 14const OAFL_CODE: i64 = 0xC00C4701 15const CDEV_CODE: i64 = 0xC0404702 16const CCV_CODE: i64 = 0xC0284704 17const CPQ_CODE: i64 = 0xC0204707 18const CSO_CODE: i64 = 0xC0604710 19const CALLOC_CODE: i64 = 0xC0484706 20const MAPVA_CODE: i64 = 0xC068470C 21const MKRES_CODE: i64 = 0xC030470B 22const SUBMIT_CODE: i64 = 0xC180470F 23 24func p(s: *u8) -> i64 { var nn: i64=0; while s[nn]!=(0 as u8){nn=nn+1} sys_write(1,s,nn); return 0 } 25func n(v: i64) -> i64 { let bb: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m;sys_write(1,"-" as *u8,1)}; let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48;k=1}; while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1}; var i: i64=0; while i<k{bb[i]=t[k-1-i];i=i+1}; sys_write(1,bb,k); return 0 } 26func x(v: i64) -> i64 { p("0x" as *u8); let bb:*u8=sys_mmap(20); var k:i64=0; var m:i64=v; if m==0{bb[0]=48;k=1}; while m>0{ let d:i64=m&15; if d<10{bb[k]=(48+d) as u8}else{bb[k]=(87+d) as u8}; m=(m>>4); k=k+1 } var i:i64=0; let o:*u8=sys_mmap(20); while i<k{o[i]=bb[k-1-i];i=i+1} sys_write(1,o,k); return 0 } 27func rd32(buf: *u8, off: i64) -> i64 { return (buf[off] as i64)|((buf[off+1] as i64)<<8)|((buf[off+2] as i64)<<16)|((buf[off+3] as i64)<<24) } 28func rd64(buf: *u8, off: i64) -> i64 { let q: *i64 = (buf as i64 + off) as *i64; return q[0] } 29func setu32(buf: *u8, off: i64, val: i64) -> i64 { let w: *u8 = (buf as i64 + off) as *u8; w[0]=(val&0xff) as u8; w[1]=((val>>8)&0xff) as u8; w[2]=((val>>16)&0xff) as u8; w[3]=((val>>24)&0xff) as u8; return 0 } 30func setu64(buf: *u8, off: i64, val: i64) -> i64 { let q: *i64 = (buf as i64 + off) as *i64; q[0]=val; return 0 } 31 32func query_type(fd: i64, handle: i64, qtype: i64, psize: i64, outv: *i64) -> i64 { 33 let priv: *u8 = sys_mmap(64); var zz: i64 = 0; while zz < 64 { priv[zz] = 0 as u8; zz = zz + 1 } 34 let req: *u8 = sys_mmap(64); var y: i64 = 0; while y < 64 { req[y] = 0 as u8; y = y + 1 } 35 let h: *i64 = (req as i64 + 0) as *i64; h[0] = (handle & 0xffffffff) | ((qtype & 0xffffffff) << 32) 36 let pd: *i64 = (req as i64 + 8) as *i64; pd[0] = priv as i64 37 let pds: *i64 = (req as i64 + 16) as *i64; pds[0] = psize & 0xffffffff 38 let ret: i64 = sys_ioctl(fd, QAI_CODE, req as i64); outv[0] = rd32(priv, 0); return ret 39} 40func open_from_luid(fd: i64, luid_lo: i64, luid_hi: i64, outh: *i64) -> i64 { 41 let req: *u8 = sys_mmap(64); var y: i64 = 0; while y < 64 { req[y] = 0 as u8; y = y + 1 } 42 let lo: *i64 = (req as i64 + 0) as *i64; lo[0] = (luid_lo & 0xffffffff) | ((luid_hi & 0xffffffff) << 32) 43 let ret: i64 = sys_ioctl(fd, OAFL_CODE, req as i64); outh[0] = rd32(req, 8); return ret 44} 45func create_device(fd: i64, adapter: i64, outd: *i64) -> i64 { 46 let buf: *u8 = sys_mmap(512); var bz: i64 = 0; while bz < 512 { buf[bz] = 0 as u8; bz = bz + 1 } 47 setu32(buf, 0, adapter & 0xffffffff) 48 let ret: i64 = sys_ioctl(fd, CDEV_CODE, buf as i64); outd[0] = rd32(buf, 12); return ret 49} 50func create_ctx(fd: i64, device: i64, outc: *i64) -> i64 { 51 let buf: *u8 = sys_mmap(512); var bz: i64 = 0; while bz < 512 { buf[bz] = 0 as u8; bz = bz + 1 } 52 setu32(buf, 0, device & 0xffffffff) 53 let ret: i64 = sys_ioctl(fd, CCV_CODE, buf as i64); outc[0] = rd32(buf, 32); return ret 54} 55func create_pq(fd: i64, device: i64, outpq: *i64) -> i64 { 56 let buf: *u8 = sys_mmap(512); var bz: i64 = 0; while bz < 512 { buf[bz] = 0 as u8; bz = bz + 1 } 57 setu32(buf, 0, device & 0xffffffff) 58 let ret: i64 = sys_ioctl(fd, CPQ_CODE, buf as i64); outpq[0] = rd32(buf, 8); return ret 59} 60// monitored fence: OUT sync_object@88, fence_cpu_va@24, fence_gpu_va@32 61func create_mf(fd: i64, device: i64, outso: *i64, outcva: *i64, outgva: *i64) -> i64 { 62 let buf: *u8 = sys_mmap(512); var bz: i64 = 0; while bz < 512 { buf[bz] = 0 as u8; bz = bz + 1 } 63 setu32(buf, 0, device & 0xffffffff); setu32(buf, 8, 5) 64 let ret: i64 = sys_ioctl(fd, CSO_CODE, buf as i64); outso[0] = rd32(buf, 88); outcva[0] = rd64(buf, 24); outgva[0] = rd64(buf, 32); return ret 65} 66func alloc_eh(fd: i64, device: i64, sysmem: *u8, outh: *i64) -> i64 { 67 let desc: *u8 = sys_mmap(64); var dz: i64 = 0; while dz < 64 { desc[dz] = 0 as u8; dz = dz + 1 } 68 setu32(desc, 0, 1); setu64(desc, 8, 65536) 69 let entry: *u8 = sys_mmap(256); var ez: i64 = 0; while ez < 256 { entry[ez] = 0 as u8; ez = ez + 1 } 70 setu64(entry, 8, sysmem as i64) 71 let buf: *u8 = sys_mmap(512); var bz: i64 = 0; while bz < 512 { buf[bz] = 0 as u8; bz = bz + 1 } 72 setu32(buf, 0, device & 0xffffffff); setu64(buf, 32, desc as i64); setu32(buf, 40, 0) 73 setu32(buf, 44, 1); setu64(buf, 48, entry as i64); setu32(buf, 56, 0x10020) 74 let ret: i64 = sys_ioctl(fd, CALLOC_CODE, buf as i64); outh[0] = rd32(entry, 0); return ret 75} 76func map_va(fd: i64, pq: i64, alloc: i64, outva: *i64) -> i64 { 77 let buf: *u8 = sys_mmap(256); var bz: i64 = 0; while bz < 256 { buf[bz] = 0 as u8; bz = bz + 1 } 78 setu32(buf, 0, pq & 0xffffffff); setu64(buf, 24, 0x10000000000) 79 setu32(buf, 32, alloc & 0xffffffff); setu64(buf, 48, 16); setu64(buf, 56, 1) 80 let ret: i64 = sys_ioctl(fd, MAPVA_CODE, buf as i64); outva[0] = rd64(buf, 88); return ret 81} 82func makeresident(fd: i64, pq: i64, alloc_handle: i64) -> i64 { 83 let alist: *u8 = sys_mmap(64); setu32(alist, 0, alloc_handle & 0xffffffff) 84 let plist: *u8 = sys_mmap(64); setu32(plist, 0, 0) 85 let buf: *u8 = sys_mmap(256); var bz: i64 = 0; while bz < 256 { buf[bz] = 0 as u8; bz = bz + 1 } 86 setu32(buf, 0, pq & 0xffffffff); setu32(buf, 4, 1); setu64(buf, 8, alist as i64); setu64(buf, 16, plist as i64) 87 return sys_ioctl(fd, MKRES_CODE, buf as i64) 88} 89 90func main() -> i64 { 91 p("=== SOVEREIGN-GPU R5a-v2: Nishi pushbuffer -> 5080 writes a MONITORED FENCE (GPU-coherent readback) ===\n" as *u8) 92 let fd: i64 = sys_openat_rd("/dev/dxg" as *u8) 93 if fd < 0 { p("open fail\n" as *u8); sys_exit(1); return 1 } 94 let ainfo: *u8 = sys_mmap(4096); var z: i64 = 0; while z < 4096 { ainfo[z] = 0 as u8; z = z + 1 } 95 let ereq: *u8 = sys_mmap(64); ereq[0] = 8 as u8; let r8: *i64 = (ereq as i64 + 8) as *i64; r8[0] = ainfo as i64 96 sys_ioctl(fd, ENUM2_CODE, ereq as i64); let nc: i64 = rd32(ereq, 0) 97 let v: *i64 = sys_mmap(16); var disc_lo: i64 = 0; var disc_hi: i64 = 0 98 var ai: i64 = 0 99 while ai < nc { 100 let base: i64 = ai * 20; let eh: i64 = rd32(ainfo, base) 101 let qret: i64 = query_type(fd, eh, 15, 4, v); let t: i64 = v[0] 102 if qret == 0 { if ((t>>4)&1) == 1 { if ((t>>2)&1) == 0 { disc_lo = rd32(ainfo, base+4); disc_hi = rd32(ainfo, base+8) } } } 103 ai = ai + 1 104 } 105 let ah: *i64 = sys_mmap(16); open_from_luid(fd, disc_lo, disc_hi, ah) 106 let dh: *i64 = sys_mmap(16); create_device(fd, ah[0], dh); let device: i64 = dh[0] 107 let chh: *i64 = sys_mmap(16); create_ctx(fd, device, chh); let context: i64 = chh[0] 108 let pqh: *i64 = sys_mmap(16); create_pq(fd, device, pqh); let pq: i64 = pqh[0] 109 let soh: *i64 = sys_mmap(16); let cva: *i64 = sys_mmap(16); let gva: *i64 = sys_mmap(16); create_mf(fd, device, soh, cva, gva) 110 let fence_cpu_va: i64 = cva[0]; let fence_gpu_va: i64 = gva[0] 111 let sm_pb: *u8 = sys_mmap(65536); var a1: i64 = 0; while a1 < 65536 { sm_pb[a1] = 0 as u8; a1 = a1 + 1 } 112 let pbh: *i64 = sys_mmap(16); alloc_eh(fd, device, sm_pb, pbh); let pb_alloc: i64 = pbh[0] 113 let pbva: *i64 = sys_mmap(16); map_va(fd, pq, pb_alloc, pbva); let pb_va: i64 = pbva[0] 114 makeresident(fd, pq, pb_alloc) 115 p(" context=" as *u8); x(context); p(" pb_va=" as *u8); x(pb_va); p(" fence_cpu_va=" as *u8); x(fence_cpu_va); p(" fence_gpu_va=" as *u8); x(fence_gpu_va); p("\n" as *u8) 116 if fence_gpu_va == 0 { p(" fence_gpu_va=0 -> monitored fence has no GPU VA; cannot target it. ABORT.\n" as *u8); sys_close(fd); return 1 } 117 118 var fence_before: i64 = 0; if fence_cpu_va != 0 { let fpp: *i64 = fence_cpu_va as *i64; fence_before = fpp[0] } 119 let PAYLOAD: i64 = 0x1234abcd 120 setu32(sm_pb, 0, 0x20050017) 121 setu32(sm_pb, 4, fence_gpu_va & 0xffffffff) 122 setu32(sm_pb, 8, (fence_gpu_va >> 32) & 0xffffffff) 123 setu32(sm_pb, 12, PAYLOAD) 124 setu32(sm_pb, 16, 0) 125 setu32(sm_pb, 20, 0x1) 126 let sb: *u8 = sys_mmap(1024); var sz: i64 = 0; while sz < 1024 { sb[sz] = 0 as u8; sz = sz + 1 } 127 setu64(sb, 0, pb_va); setu32(sb, 8, 24); setu32(sb, 0x18, 1); setu32(sb, 0x1c, context & 0xffffffff) 128 let sr: i64 = sys_ioctl(fd, SUBMIT_CODE, sb as i64) 129 p(" fence_before=" as *u8); x(fence_before); p(" SUBMITCOMMAND ret=" as *u8); n(sr); p("\n" as *u8) 130 131 let fpp: *i64 = fence_cpu_va as *i64 132 var iters: i64 = 0; var hit: i64 = 0 133 while iters < 400000000 { let cur: i64 = fpp[0]; if (cur & 0xffffffff) == PAYLOAD { hit = 1; iters = 400000000 } else { iters = iters + 1 } } 134 let final: i64 = fpp[0] 135 p(" fence CPU value after submit = " as *u8); x(final); p(" expected low32=" as *u8); x(PAYLOAD); p("\n" as *u8) 136 if (final & 0xffffffff) == PAYLOAD { p(" *** THE RTX 5080 EXECUTED OUR SOVEREIGN PUSHBUFFER (fence written via GPU semaphore) ***\n" as *u8) } 137 else { p(" (GPU write not observed on the fence -- if fence stays " as *u8); x(fence_before); p(", H2 [host translates cmd buffer / not raw pushbuffer] is the wall)\n" as *u8) } 138 sys_close(fd) 139 p("=== R5a-v2 DONE ===\n" as *u8) 140 return 0 141}