_gpu_oplist_gate.nx

_gpu_oplist_gate.nx -- GPU-class driver-from-spec gate (X-DRV-W1 -> X-DRV-003 / GPU trajectory): the 4th device class as a GENERIC op-list on the CANONICAL emitter nx_drv_proto_emit, composing with the sovereign SPIR-V lane. Proves: (1) GPU -- the GENERIC nx_drv_proto_emit, driven by knowledge/specs/gpu_dispatch_virt.spec alone (zero emitter change), authors a GPU-class command-submission driver; the SOVEREIGN rv64 emu (+ the rv64im_min_gpu device model, via the dedicated _gpu_run runner) runs it: CTRL.EN -> confirm STATUS.READY -> bind the command ring -> lay a command packet carrying the SPIR-V magic 0x07230203 -> ring the DOORBELL -> device validates the SPIR-V magic, signals the FENCE + latches RESULTPEEK -> driver verifies FENCE==seqno and RESULTPEEK==(operand<<16)|seqno. Serial CONTAINS golden "GPUENRINGCMDFENCE" + a clean halt (BOOTSOV verdict=GREEN). (2) DISTINCT -- the SAME emitter binary, driven by the NVMe op-list, yields a DIFFERENT golden; the GPU class is just-a-spec, not NVMe/virtio in disguise. (3) TAMPER x2 on the GPU image: bump the device-base lui imm (byte 7) -> all MMIO targets a non- device address -> the ID identity verify fails -> transcript collapses; bump the ID-expected li high byte (byte 15) -> identity mismatch -> collapses. Each must drop the golden. Every verdict is a PRINTED marker off a REAL sovereign run; raw bytes read SOVEREIGNLY (sys_read). NO qemu/gcc/openssl/python. Marker -> knowledge/status/driver_spec.log (GPUOPGATE row). Sovereign orchestration (fork/dup3/execve/wait4). license_tier: ORIGINAL