_gpu_dxg_pagingqueue_gate.nx

_gpu_dxg_pagingqueue_gate.nx -- SOVEREIGN-GPU ladder R4c (create a GPU PAGING QUEUE + fence on the 5080). R4b read the real VRAM budget. R4c creates the WDDM residency-manager object (the paging queue) that GPU memory is paged/made-resident against via LX_DXCREATEPAGINGQUEUE -- and the kernel mmaps a FENCE PAGE into our address space for lock-free CPU<->GPU fence polling. This is the residency substrate for real allocations (R4d) + command submission (R4e). ABI (recon-pinned LIVE, _gpu_dxg_r4c_pq_recon: no uapi header -> size-swept, only _IOC_SIZE=32 recognized; OUT offsets located by dump): LX_DXCREATEPAGINGQUEUE = _IOWR(0x47, 0x07, 32) = 0xC0204707 struct (32B): device @0 (in); priority @4 (in, 0=NORMAL); paging_queue @8 (OUT); sync_object @12 (OUT); fence_cpu_virtual_address @16 (u64, OUT -- a REAL page the kernel maps into us); physical_adapter_index @24 (in). GREEN iff (author=organ, from REAL device returns): A) device-create chain ok (enum/discrete/open-adapter/create-device all ret==0); B) CREATEPAGINGQUEUE #1 ret==0 AND paging_queue!=0 AND sync_object!=0 AND fence_VA!=0 (all written into pre-zeroed slots) AND fence_VA is a canonical userspace addr (<0x800000000000); C) the fence page is GENUINELY MAPPED: we DEREFERENCE fence_VA and read its u64 fence value -- if the VA were bogus the process would fault and never reach GREEN, so reaching the verdict after the read IS the proof; D) CREATEPAGINGQUEUE #2 ret==0 AND paging_queue2!=0 AND paging_queue2 != paging_queue1 (per-call allocation); E) TAMPER: T1 bogus device(0xdeadbeef) -> ret!=0 AND paging_queue stays 0; T2 wrong _IOC_SIZE(28) -> -ENOTTY; T3 on a non-dxg fd -> -ENOTTY. Marker -> knowledge/status/gpu_dxg.log (DXGPQGATE). raw syscalls only. NO-WAVE: creates a residency object + reads a fence page; NO compute/throughput claimed (that is R7). license_tier: ORIGINAL