_gpu_bm_compute_gate.nx

_gpu_bm_compute_gate.nx -- BARE-METAL SOVEREIGN-GPU rung BM-GPU-C1: compute-class dispatch + GEMM through the sovereign GPFIFO pipeline (model side, toward BM-GPU-7). Extends the FIFO model with engine-class binding: NVC56F_SET_OBJECT @0x0 (REAL FIFO method) binds a class id to a subchannel; methods on a COMPUTE-bound subchannel route to a modeled compute engine. A sovereign driver fills matrices A,B in modeled VRAM, emits a compute-dispatch pushbuffer (SET_OBJECT compute + matrix addrs/dims + LAUNCH), and the modeled engine runs C = A*B, writing C to its GPU VA. The driver reads C and checks it against an INDEPENDENT reference GEMM -> proves the compute COMMAND STREAM was decoded + dispatched correctly. NISHI-ECOSYSTEM-ONLY: our model+driver+command-stream. HONEST SCOPE: SET_OBJECT/class-bind is spec-faithful; the compute-class method OFFSETS here are REPRESENTATIVE (the production NVC6C0/Blackwell QMD + a real SASS GEMM kernel is BM-GPU-7 on real silicon). The modeled engine STANDS IN for SASS execution. This gates the dispatch+result LOGIC. GREEN iff: after the dispatch, C == independent reference GEMM (4x4 int); AND tampers (no SET_OBJECT class-bind / no LAUNCH) leave C unwritten (dispatch is gated on class-bind + launch). Marker -> knowledge/status/gpu_baremetal.log (BMCOMPUTEGATE). license_tier: ORIGINAL