nx_gpu_sync_gate.nx

nx_gpu_sync_gate.nx -- the sovereign GPU fence (nx_gpu_sync gpu_sync_fence) on the real device, driven directly. gpu GP7, the FENCE half: a monitored fence created on the discrete 5080 through raw /dev/dxg, signalled from the CPU and waited on synchronously -- the round trip completes only when the signals advanced the real fence. Teeth: the device resolves; the fence round-trips; an invalid sync-object type is REFUSED (the create is type-sensitive, not a blind success); three tampers are rejected (a bogus handle, a zero object count, a non-dxg fd); and a POSITIVE CONTROL after the tampers still round-trips, so this is not a guard that refuses everything. THE THIRD STATE: the subject is a physical device most hosts lack (the NAS that builds this has no /dev/dxg). Absent hardware is a gv_need precondition -> SKIP, never RED; a RED from this gate means the fence path broke. The BARRIER half of GP7 is not claimed here (see nx_gpu_sync.nx); the board carries that scope. license_tier: ORIGINAL No hw writes (Rule 26). expect_exit: 0 (or 3 = SKIP where there is no /dev/dxg)