code wiki / _hdl_build / nx_dxg.nx

nx_dxg.nx

buildroot/runtime/_hdl_build/nx_dxg.nx

6754 B100 linesdepth 2pulls 2 transitivereach 2 importersview sourcekind library
docsdependenciesstructsconstsfunctions

about

nx_dxg.nx -- the /dev/dxg DEVICE-HAL SHIM (WSL2 GPU-PV backend), CONSOLIDATED. The dxg control-plane (enumerate adapters, query type, open device, create context/paging-queue, alloc, map-VA, make-resident, hardware-queue create/submit) was COPY-PASTED across _gpu_dxg_r5a_sem, _gpu_dxg_r6_hwq, and nx_device_probe. This lib is the single source of truth -- pure funcs, no main. It is ONE per-OS device shim (mirrors nx_hal's per-target shim model); native-Linux /dev/dri = a sibling shim implementing the same interface, so the per-device backends above it don't change. license_tier: ORIGINAL

dependencies 1 imports · 2 importers

nx_syscalls.nx nx_dxg.nx _gpu_dxg_r6_hwq.nx nx_device_probe.nx

imports: nx_syscalls.nx

imported by: _gpu_dxg_r6_hwq.nxnx_device_probe.nx

structs

none

consts

9const DXG_MAGIC_4096: i64 = 4096
10const DXG_MAGIC_65536: i64 = 65536
12const DXG_ENUM2: i64 = 0xC0104714
13const DXG_QAI: i64 = 0xC0184709
14const DXG_OAFL: i64 = 0xC00C4701
15const DXG_CDEV: i64 = 0xC0404702
16const DXG_CCV: i64 = 0xC0284704
17const DXG_CPQ: i64 = 0xC0204707
18const DXG_CALLOC: i64 = 0xC0484706
19const DXG_MAPVA: i64 = 0xC068470C
20const DXG_MKRES: i64 = 0xC030470B
21const DXG_CHWQ: i64 = 0xC0304718
22const DXG_SUBHWQ: i64 = 0xC0384734

functions

24func dxg_rd32(buf: *u8, off: i64) -> i64 { return (buf[off] as i64)|((buf[off+1] as i64)<<8)|((buf[off+2] as i64)<<16)|((buf[off+3] as i64)<<24) }
called by 10: mainmaindxg_enumdxg_query_typedxg_open_from_luiddxg_create_device+4
25func dxg_rd64(buf: *u8, off: i64) -> i64 { let q: *i64 = (buf as i64 + off) as *i64; return q[0] }
called by 4: dxg_create_pqdxg_map_vadxg_makeresidentdxg_create_hwqueue
26func dxg_setu32(buf: *u8, off: i64, val: i64) -> i64 { let w: *u8 = (buf as i64 + off) as *u8; w[0]=(val&0xff) as u8; w[1]=((val>>8)&0xff) as u8; w[2]=((val>>16)&0xff) as u8; w[3]=((val>>24)&0xff) as u8; return 0 }
called by 9: maindxg_create_devicedxg_create_ctxdxg_create_pqdxg_alloc_ehdxg_map_va+3
27func dxg_setu64(buf: *u8, off: i64, val: i64) -> i64 { let q: *i64 = (buf as i64 + off) as *i64; q[0]=val; return 0 }
called by 4: dxg_alloc_ehdxg_map_vadxg_makeresidentdxg_submit_hwq
29func dxg_open() -> i64 { return sys_openat_rd("/dev/dxg" as *u8) }
called by 2: mainmain calls 1: sys_openat_rd
31func dxg_enum(fd: i64, ainfo: *u8) -> i64
called by 2: mainmain calls 3: sys_mmapsys_ioctldxg_rd32
37func dxg_query_type(fd: i64, handle: i64, qtype: i64, psize: i64, outv: *i64) -> i64
called by 2: mainmain calls 3: sys_mmapsys_ioctldxg_rd32
45func dxg_open_from_luid(fd: i64, luid_lo: i64, luid_hi: i64, outh: *i64) -> i64
called by 1: main calls 3: sys_mmapsys_ioctldxg_rd32
50func dxg_create_device(fd: i64, adapter: i64, outd: *i64) -> i64
called by 1: main calls 4: sys_mmapdxg_setu32sys_ioctldxg_rd32
55func dxg_create_ctx(fd: i64, device: i64, outc: *i64) -> i64
called by 1: main calls 4: sys_mmapdxg_setu32sys_ioctldxg_rd32
60func dxg_create_pq(fd: i64, device: i64, outpq: *i64, outfva: *i64) -> i64
called by 1: main calls 5: sys_mmapdxg_setu32sys_ioctldxg_rd32dxg_rd64
65func dxg_alloc_eh(fd: i64, device: i64, sysmem: *u8, outh: *i64) -> i64
called by 1: main calls 5: sys_mmapdxg_setu32dxg_setu64sys_ioctldxg_rd32
75func dxg_map_va(fd: i64, pq: i64, alloc: i64, outva: *i64, outf: *i64) -> i64
called by 1: main calls 5: sys_mmapdxg_setu32dxg_setu64sys_ioctldxg_rd64
81func dxg_makeresident(fd: i64, pq: i64, alloc_handle: i64, outf: *i64) -> i64
called by 1: main calls 5: sys_mmapdxg_setu32dxg_setu64sys_ioctldxg_rd64
88func dxg_create_hwqueue(fd: i64, context: i64, outq: *i64, outfgva: *i64, outfcva: *i64) -> i64
called by 1: main calls 5: sys_mmapdxg_setu32sys_ioctldxg_rd32dxg_rd64
95func dxg_submit_hwq(fd: i64, hwqueue: i64, cmd_va: i64, cmd_len: i64, fence_id: i64) -> i64
called by 1: main calls 4: sys_mmapdxg_setu32dxg_setu64sys_ioctl