nx_dxg.nx source

1// nx_dxg.nx -- the /dev/dxg DEVICE-HAL SHIM (WSL2 GPU-PV backend), CONSOLIDATED. 2// 3// The dxg control-plane (enumerate adapters, query type, open device, create context/paging-queue, alloc, 4// map-VA, make-resident, hardware-queue create/submit) was COPY-PASTED across _gpu_dxg_r5a_sem, 5// _gpu_dxg_r6_hwq, and nx_device_probe. This lib is the single source of truth -- pure funcs, no main. 6// It is ONE per-OS device shim (mirrors nx_hal's per-target shim model); native-Linux /dev/dri = a sibling 7// shim implementing the same interface, so the per-device backends above it don't change. license_tier: ORIGINAL 8import "nx_syscalls.nx" 9const DXG_MAGIC_4096: i64 = 4096 10const DXG_MAGIC_65536: i64 = 65536 11 12const DXG_ENUM2: i64 = 0xC0104714 13const DXG_QAI: i64 = 0xC0184709 14const DXG_OAFL: i64 = 0xC00C4701 15const DXG_CDEV: i64 = 0xC0404702 16const DXG_CCV: i64 = 0xC0284704 17const DXG_CPQ: i64 = 0xC0204707 18const DXG_CALLOC: i64 = 0xC0484706 19const DXG_MAPVA: i64 = 0xC068470C 20const DXG_MKRES: i64 = 0xC030470B 21const DXG_CHWQ: i64 = 0xC0304718 22const DXG_SUBHWQ: i64 = 0xC0384734 23 24func dxg_rd32(buf: *u8, off: i64) -> i64 { return (buf[off] as i64)|((buf[off+1] as i64)<<8)|((buf[off+2] as i64)<<16)|((buf[off+3] as i64)<<24) } 25func dxg_rd64(buf: *u8, off: i64) -> i64 { let q: *i64 = (buf as i64 + off) as *i64; return q[0] } 26func dxg_setu32(buf: *u8, off: i64, val: i64) -> i64 { let w: *u8 = (buf as i64 + off) as *u8; w[0]=(val&0xff) as u8; w[1]=((val>>8)&0xff) as u8; w[2]=((val>>16)&0xff) as u8; w[3]=((val>>24)&0xff) as u8; return 0 } 27func dxg_setu64(buf: *u8, off: i64, val: i64) -> i64 { let q: *i64 = (buf as i64 + off) as *i64; q[0]=val; return 0 } 28 29func dxg_open() -> i64 { return sys_openat_rd("/dev/dxg" as *u8) } 30// enumerate adapters into caller-provided ainfo (>=4096 bytes); returns adapter count. 31func dxg_enum(fd: i64, ainfo: *u8) -> i64 { 32 var z: i64 = 0; while z < DXG_MAGIC_4096 { ainfo[z] = 0 as u8; z = z + 1 } 33 let ereq: *u8 = sys_mmap(64); ereq[0] = 8 as u8; let r8: *i64 = (ereq as i64 + 8) as *i64; r8[0] = ainfo as i64 34 sys_ioctl(fd, DXG_ENUM2, ereq as i64) 35 return dxg_rd32(ereq, 0) 36} 37func dxg_query_type(fd: i64, handle: i64, qtype: i64, psize: i64, outv: *i64) -> i64 { 38 let priv: *u8 = sys_mmap(64); var zz: i64 = 0; while zz < 64 { priv[zz] = 0 as u8; zz = zz + 1 } 39 let req: *u8 = sys_mmap(64); var y: i64 = 0; while y < 64 { req[y] = 0 as u8; y = y + 1 } 40 let h: *i64 = (req as i64 + 0) as *i64; h[0] = (handle & 0xffffffff) | ((qtype & 0xffffffff) << 32) 41 let pd: *i64 = (req as i64 + 8) as *i64; pd[0] = priv as i64 42 let pds: *i64 = (req as i64 + 16) as *i64; pds[0] = psize & 0xffffffff 43 let ret: i64 = sys_ioctl(fd, DXG_QAI, req as i64); outv[0] = dxg_rd32(priv, 0); return ret 44} 45func dxg_open_from_luid(fd: i64, luid_lo: i64, luid_hi: i64, outh: *i64) -> i64 { 46 let req: *u8 = sys_mmap(64); var y: i64 = 0; while y < 64 { req[y] = 0 as u8; y = y + 1 } 47 let lo: *i64 = (req as i64 + 0) as *i64; lo[0] = (luid_lo & 0xffffffff) | ((luid_hi & 0xffffffff) << 32) 48 let ret: i64 = sys_ioctl(fd, DXG_OAFL, req as i64); outh[0] = dxg_rd32(req, 8); return ret 49} 50func dxg_create_device(fd: i64, adapter: i64, outd: *i64) -> i64 { 51 let buf: *u8 = sys_mmap(512); var bz: i64 = 0; while bz < 512 { buf[bz] = 0 as u8; bz = bz + 1 } 52 dxg_setu32(buf, 0, adapter & 0xffffffff) 53 let ret: i64 = sys_ioctl(fd, DXG_CDEV, buf as i64); outd[0] = dxg_rd32(buf, 12); return ret 54} 55func dxg_create_ctx(fd: i64, device: i64, outc: *i64) -> i64 { 56 let buf: *u8 = sys_mmap(512); var bz: i64 = 0; while bz < 512 { buf[bz] = 0 as u8; bz = bz + 1 } 57 dxg_setu32(buf, 0, device & 0xffffffff) 58 let ret: i64 = sys_ioctl(fd, DXG_CCV, buf as i64); outc[0] = dxg_rd32(buf, 32); return ret 59} 60func dxg_create_pq(fd: i64, device: i64, outpq: *i64, outfva: *i64) -> i64 { 61 let buf: *u8 = sys_mmap(512); var bz: i64 = 0; while bz < 512 { buf[bz] = 0 as u8; bz = bz + 1 } 62 dxg_setu32(buf, 0, device & 0xffffffff) 63 let ret: i64 = sys_ioctl(fd, DXG_CPQ, buf as i64); outpq[0] = dxg_rd32(buf, 8); outfva[0] = dxg_rd64(buf, 16); return ret 64} 65func dxg_alloc_eh(fd: i64, device: i64, sysmem: *u8, outh: *i64) -> i64 { 66 let desc: *u8 = sys_mmap(64); var dz: i64 = 0; while dz < 64 { desc[dz] = 0 as u8; dz = dz + 1 } 67 dxg_setu32(desc, 0, 1); dxg_setu64(desc, 8, DXG_MAGIC_65536) 68 let entry: *u8 = sys_mmap(256); var ez: i64 = 0; while ez < 256 { entry[ez] = 0 as u8; ez = ez + 1 } 69 dxg_setu64(entry, 8, sysmem as i64) 70 let buf: *u8 = sys_mmap(512); var bz: i64 = 0; while bz < 512 { buf[bz] = 0 as u8; bz = bz + 1 } 71 dxg_setu32(buf, 0, device & 0xffffffff); dxg_setu64(buf, 32, desc as i64); dxg_setu32(buf, 40, 0) 72 dxg_setu32(buf, 44, 1); dxg_setu64(buf, 48, entry as i64); dxg_setu32(buf, 56, 0x10020) 73 let ret: i64 = sys_ioctl(fd, DXG_CALLOC, buf as i64); outh[0] = dxg_rd32(entry, 0); return ret 74} 75func dxg_map_va(fd: i64, pq: i64, alloc: i64, outva: *i64, outf: *i64) -> i64 { 76 let buf: *u8 = sys_mmap(256); var bz: i64 = 0; while bz < 256 { buf[bz] = 0 as u8; bz = bz + 1 } 77 dxg_setu32(buf, 0, pq & 0xffffffff); dxg_setu64(buf, 24, 0x10000000000) 78 dxg_setu32(buf, 32, alloc & 0xffffffff); dxg_setu64(buf, 48, 16); dxg_setu64(buf, 56, 1) 79 let ret: i64 = sys_ioctl(fd, DXG_MAPVA, buf as i64); outva[0] = dxg_rd64(buf, 88); outf[0] = dxg_rd64(buf, 96); return ret 80} 81func dxg_makeresident(fd: i64, pq: i64, alloc_handle: i64, outf: *i64) -> i64 { 82 let alist: *u8 = sys_mmap(64); dxg_setu32(alist, 0, alloc_handle & 0xffffffff) 83 let plist: *u8 = sys_mmap(64); dxg_setu32(plist, 0, 0) 84 let buf: *u8 = sys_mmap(256); var bz: i64 = 0; while bz < 256 { buf[bz] = 0 as u8; bz = bz + 1 } 85 dxg_setu32(buf, 0, pq & 0xffffffff); dxg_setu32(buf, 4, 1); dxg_setu64(buf, 8, alist as i64); dxg_setu64(buf, 16, plist as i64) 86 let ret: i64 = sys_ioctl(fd, DXG_MKRES, buf as i64); outf[0] = dxg_rd64(buf, 32); return ret 87} 88func dxg_create_hwqueue(fd: i64, context: i64, outq: *i64, outfgva: *i64, outfcva: *i64) -> i64 { 89 let buf: *u8 = sys_mmap(512); var bz: i64 = 0; while bz < 512 { buf[bz] = 0 as u8; bz = bz + 1 } 90 dxg_setu32(buf, 0, context & 0xffffffff) 91 let ret: i64 = sys_ioctl(fd, DXG_CHWQ, buf as i64) 92 outq[0] = dxg_rd32(buf, 24); outfcva[0] = dxg_rd64(buf, 32); outfgva[0] = dxg_rd64(buf, 40) 93 return ret 94} 95func dxg_submit_hwq(fd: i64, hwqueue: i64, cmd_va: i64, cmd_len: i64, fence_id: i64) -> i64 { 96 let buf: *u8 = sys_mmap(256); var bz: i64 = 0; while bz < 256 { buf[bz] = 0 as u8; bz = bz + 1 } 97 dxg_setu32(buf, 0, hwqueue & 0xffffffff); dxg_setu64(buf, 8, fence_id); dxg_setu64(buf, 16, cmd_va); dxg_setu32(buf, 24, cmd_len & 0xffffffff) 98 let ret: i64 = sys_ioctl(fd, DXG_SUBHWQ, buf as i64) 99 return ret 100}