nx_gpu_sync.nx

nx_gpu_sync.nx -- the sovereign GPU FENCE over the dxg door (gpu GP7, the fence half of "fences and barriers"). A monotonic timeline fence the CPU can signal and wait on, as ONE composed primitive over the nx_dxg shim: gpu_sync_fence creates a MONITORED_FENCE sync object on the device, signals it to 1 and then to 2, and waits for 2 -- a round trip that only completes when the signals advanced the real fence. It returns 0 on the round trip, a NEGATIVE code naming the stage that refused, and leaves the sync-object handle in outso[0] so a caller that wants the fence for real work keeps it. PROVENANCE: the ABI and the round-trip were measured LIVE on the RTX 5080 by the R4g candidate gate (_offc/cand__gpu_dxg_syncobj_gate, size-swept ioctl codes, type-99 refused, three tampers rejected) and sat unpromoted for weeks. Folded here so the estate has ONE fence primitive and ONE gate over it (nx_gpu_sync_gate). The BARRIER half of GP7 (a barrier a recorded list carries between a write and a read) is NOT here: it needs a command list the dxg door can execute, which the raw channel cannot carry without a vendor UMD (gpu.plan GP5 lesson row, 2026-09-02). This file is the fence; the board says which half. SCOPE: /dev/dxg only (WSL2 GPU-PV). No third party in the run path: raw ioctls through nx_syscalls. license_tier: ORIGINAL No hw writes (Rule 26): sync objects are per-process kernel state, never persistent.