code wiki / _hdl_build / _gpu_dxg_r5a_sem.nx
_gpu_dxg_r5a_sem.nx
buildroot/runtime/_hdl_build/_gpu_dxg_r5a_sem.nx
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_gpu_dxg_r5a_sem.nx -- SOVEREIGN-GPU R5a: make the real RTX 5080 EXECUTE a Nishi-emitted pushbuffer.
HARDWARE-RUNG-UP, NISHI-ECOSYSTEM-ONLY: Nishi EMITS the raw NVIDIA host/FIFO semaphore-release pushbuffer
ITSELF (the GPU's native command format is the last-mile hardware protocol, learned from the open spec but
emitted sovereignly -- NO libcuda/Mesa/NVIDIA software linked or called). The GPU writes a known payload to a
GPU VA backed by our EXISTINGHEAP system memory; we read it back CPU-side = the GPU ran OUR commands.
Pushbuffer (GF100 method header = (mode<<29)|(count<<16)|(subch<<13)|(method>>2)); host-method semaphore release
(NVC56F, stable Ampere->Blackwell): SEM_ADDR_LO@0x5c, SEM_ADDR_HI@0x60, SEM_PAYLOAD_LO@0x64, SEM_PAYLOAD_HI@0x68,
SEM_EXECUTE@0x6c (OPERATION_RELEASE=1, PAYLOAD_SIZE_32BIT=0 -> value 0x1). 6 dwords:
[0]=0x20050017 (increasing,count=5,subch0,method 0x5c>>2=0x17) [1]=addr_lo [2]=addr_hi [3]=payload [4]=0 [5]=0x1
SUBMITCOMMAND = 0xC180470F (size 384, size-swept): command_buffer@0=pushbuffer GPU VA, command_length@8,
broadcast_context_count@0x18=1, broadcast_context[0]@0x20=context. RISK: a malformed submit may TDR (WSL recovers).
license_tier: ORIGINAL
dependencies 1 imports · 0 importers
imports: nx_syscalls.nx
imported by: nobody (leaf or entry point)
call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown
structs
| none |
consts
| 17 | const ENUM2_CODE: i64 = 0xC0104714 |
| 18 | const QAI_CODE: i64 = 0xC0184709 |
| 19 | const OAFL_CODE: i64 = 0xC00C4701 |
| 20 | const CDEV_CODE: i64 = 0xC0404702 |
| 21 | const CCV_CODE: i64 = 0xC0284704 |
| 22 | const CPQ_CODE: i64 = 0xC0204707 |
| 23 | const CALLOC_CODE: i64 = 0xC0484706 |
| 24 | const MAPVA_CODE: i64 = 0xC068470C |
| 25 | const MKRES_CODE: i64 = 0xC030470B |
| 26 | const SUBMIT_CODE: i64 = 0xC180470F |
functions
| 28 | func p(s: *u8) -> i64 { var nn: i64=0; while s[nn]!=(0 as u8){nn=nn+1} sys_write(1,s,nn); return 0 } |
| 29 | func n(v: i64) -> i64 { let bb: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m;sys_write(1,"-" as *u8,1)}; let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48;k=1}; while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1}; var i: i64=0; while i<k{bb[i]=t[k-1-i];i=i+1}; sys_write(1,bb,k); return 0 } |
| 30 | func x(v: i64) -> i64 { p("0x" as *u8); let bb:*u8=sys_mmap(20); var k:i64=0; var m:i64=v; if m==0{bb[0]=48;k=1}; while m>0{ let d:i64=m&15; if d<10{bb[k]=(48+d) as u8}else{bb[k]=(87+d) as u8}; m=(m>>4); k=k+1 } var i:i64=0; let o:*u8=sys_mmap(20); while i<k{o[i]=bb[k-1-i];i=i+1} sys_write(1,o,k); return 0 } |
| 31 | func rd32(buf: *u8, off: i64) -> i64 { return (buf[off] as i64)|((buf[off+1] as i64)<<8)|((buf[off+2] as i64)<<16)|((buf[off+3] as i64)<<24) } |
| 32 | func rd64(buf: *u8, off: i64) -> i64 { let q: *i64 = (buf as i64 + off) as *i64; return q[0] } |
| 33 | func setu32(buf: *u8, off: i64, val: i64) -> i64 { let w: *u8 = (buf as i64 + off) as *u8; w[0]=(val&0xff) as u8; w[1]=((val>>8)&0xff) as u8; w[2]=((val>>16)&0xff) as u8; w[3]=((val>>24)&0xff) as u8; return 0 } |
| 34 | func setu64(buf: *u8, off: i64, val: i64) -> i64 { let q: *i64 = (buf as i64 + off) as *i64; q[0]=val; return 0 } |
| 36 | func query_type(fd: i64, handle: i64, qtype: i64, psize: i64, outv: *i64) -> i64 |
| 44 | func open_from_luid(fd: i64, luid_lo: i64, luid_hi: i64, outh: *i64) -> i64 |
| 49 | func create_device(fd: i64, adapter: i64, outd: *i64) -> i64 |
| 54 | func create_ctx(fd: i64, device: i64, outc: *i64) -> i64 |
| 59 | func create_pq(fd: i64, device: i64, outpq: *i64, outfva: *i64) -> i64 |
| 64 | func alloc_eh(fd: i64, device: i64, sysmem: *u8, outh: *i64) -> i64 |
| 74 | func map_va(fd: i64, pq: i64, alloc: i64, outva: *i64, outf: *i64) -> i64 |
| 80 | func makeresident(fd: i64, pq: i64, alloc_handle: i64, outf: *i64) -> i64 |
| 87 | func wait_fence(fence_va: i64, target: i64) -> i64 called by 1: main |
| 93 | func main() -> i64 |