_gpu_dxg_r5a_sem.nx source

1// _gpu_dxg_r5a_sem.nx -- SOVEREIGN-GPU R5a: make the real RTX 5080 EXECUTE a Nishi-emitted pushbuffer. 2// 3// HARDWARE-RUNG-UP, NISHI-ECOSYSTEM-ONLY: Nishi EMITS the raw NVIDIA host/FIFO semaphore-release pushbuffer 4// ITSELF (the GPU's native command format is the last-mile hardware protocol, learned from the open spec but 5// emitted sovereignly -- NO libcuda/Mesa/NVIDIA software linked or called). The GPU writes a known payload to a 6// GPU VA backed by our EXISTINGHEAP system memory; we read it back CPU-side = the GPU ran OUR commands. 7// 8// Pushbuffer (GF100 method header = (mode<<29)|(count<<16)|(subch<<13)|(method>>2)); host-method semaphore release 9// (NVC56F, stable Ampere->Blackwell): SEM_ADDR_LO@0x5c, SEM_ADDR_HI@0x60, SEM_PAYLOAD_LO@0x64, SEM_PAYLOAD_HI@0x68, 10// SEM_EXECUTE@0x6c (OPERATION_RELEASE=1, PAYLOAD_SIZE_32BIT=0 -> value 0x1). 6 dwords: 11// [0]=0x20050017 (increasing,count=5,subch0,method 0x5c>>2=0x17) [1]=addr_lo [2]=addr_hi [3]=payload [4]=0 [5]=0x1 12// SUBMITCOMMAND = 0xC180470F (size 384, size-swept): command_buffer@0=pushbuffer GPU VA, command_length@8, 13// broadcast_context_count@0x18=1, broadcast_context[0]@0x20=context. RISK: a malformed submit may TDR (WSL recovers). 14// license_tier: ORIGINAL 15import "nx_syscalls.nx" 16 17const ENUM2_CODE: i64 = 0xC0104714 18const QAI_CODE: i64 = 0xC0184709 19const OAFL_CODE: i64 = 0xC00C4701 20const CDEV_CODE: i64 = 0xC0404702 21const CCV_CODE: i64 = 0xC0284704 22const CPQ_CODE: i64 = 0xC0204707 23const CALLOC_CODE: i64 = 0xC0484706 24const MAPVA_CODE: i64 = 0xC068470C 25const MKRES_CODE: i64 = 0xC030470B 26const SUBMIT_CODE: i64 = 0xC180470F 27 28func p(s: *u8) -> i64 { var nn: i64=0; while s[nn]!=(0 as u8){nn=nn+1} sys_write(1,s,nn); return 0 } 29func n(v: i64) -> i64 { let bb: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m;sys_write(1,"-" as *u8,1)}; let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48;k=1}; while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1}; var i: i64=0; while i<k{bb[i]=t[k-1-i];i=i+1}; sys_write(1,bb,k); return 0 } 30func x(v: i64) -> i64 { p("0x" as *u8); let bb:*u8=sys_mmap(20); var k:i64=0; var m:i64=v; if m==0{bb[0]=48;k=1}; while m>0{ let d:i64=m&15; if d<10{bb[k]=(48+d) as u8}else{bb[k]=(87+d) as u8}; m=(m>>4); k=k+1 } var i:i64=0; let o:*u8=sys_mmap(20); while i<k{o[i]=bb[k-1-i];i=i+1} sys_write(1,o,k); return 0 } 31func rd32(buf: *u8, off: i64) -> i64 { return (buf[off] as i64)|((buf[off+1] as i64)<<8)|((buf[off+2] as i64)<<16)|((buf[off+3] as i64)<<24) } 32func rd64(buf: *u8, off: i64) -> i64 { let q: *i64 = (buf as i64 + off) as *i64; return q[0] } 33func setu32(buf: *u8, off: i64, val: i64) -> i64 { let w: *u8 = (buf as i64 + off) as *u8; w[0]=(val&0xff) as u8; w[1]=((val>>8)&0xff) as u8; w[2]=((val>>16)&0xff) as u8; w[3]=((val>>24)&0xff) as u8; return 0 } 34func setu64(buf: *u8, off: i64, val: i64) -> i64 { let q: *i64 = (buf as i64 + off) as *i64; q[0]=val; return 0 } 35 36func query_type(fd: i64, handle: i64, qtype: i64, psize: i64, outv: *i64) -> i64 { 37 let priv: *u8 = sys_mmap(64); var zz: i64 = 0; while zz < 64 { priv[zz] = 0 as u8; zz = zz + 1 } 38 let req: *u8 = sys_mmap(64); var y: i64 = 0; while y < 64 { req[y] = 0 as u8; y = y + 1 } 39 let h: *i64 = (req as i64 + 0) as *i64; h[0] = (handle & 0xffffffff) | ((qtype & 0xffffffff) << 32) 40 let pd: *i64 = (req as i64 + 8) as *i64; pd[0] = priv as i64 41 let pds: *i64 = (req as i64 + 16) as *i64; pds[0] = psize & 0xffffffff 42 let ret: i64 = sys_ioctl(fd, QAI_CODE, req as i64); outv[0] = rd32(priv, 0); return ret 43} 44func open_from_luid(fd: i64, luid_lo: i64, luid_hi: i64, outh: *i64) -> i64 { 45 let req: *u8 = sys_mmap(64); var y: i64 = 0; while y < 64 { req[y] = 0 as u8; y = y + 1 } 46 let lo: *i64 = (req as i64 + 0) as *i64; lo[0] = (luid_lo & 0xffffffff) | ((luid_hi & 0xffffffff) << 32) 47 let ret: i64 = sys_ioctl(fd, OAFL_CODE, req as i64); outh[0] = rd32(req, 8); return ret 48} 49func create_device(fd: i64, adapter: i64, outd: *i64) -> i64 { 50 let buf: *u8 = sys_mmap(512); var bz: i64 = 0; while bz < 512 { buf[bz] = 0 as u8; bz = bz + 1 } 51 setu32(buf, 0, adapter & 0xffffffff) 52 let ret: i64 = sys_ioctl(fd, CDEV_CODE, buf as i64); outd[0] = rd32(buf, 12); return ret 53} 54func create_ctx(fd: i64, device: i64, outc: *i64) -> i64 { 55 let buf: *u8 = sys_mmap(512); var bz: i64 = 0; while bz < 512 { buf[bz] = 0 as u8; bz = bz + 1 } 56 setu32(buf, 0, device & 0xffffffff) 57 let ret: i64 = sys_ioctl(fd, CCV_CODE, buf as i64); outc[0] = rd32(buf, 32); return ret 58} 59func create_pq(fd: i64, device: i64, outpq: *i64, outfva: *i64) -> i64 { 60 let buf: *u8 = sys_mmap(512); var bz: i64 = 0; while bz < 512 { buf[bz] = 0 as u8; bz = bz + 1 } 61 setu32(buf, 0, device & 0xffffffff) 62 let ret: i64 = sys_ioctl(fd, CPQ_CODE, buf as i64); outpq[0] = rd32(buf, 8); outfva[0] = rd64(buf, 16); return ret 63} 64func alloc_eh(fd: i64, device: i64, sysmem: *u8, outh: *i64) -> i64 { 65 let desc: *u8 = sys_mmap(64); var dz: i64 = 0; while dz < 64 { desc[dz] = 0 as u8; dz = dz + 1 } 66 setu32(desc, 0, 1); setu64(desc, 8, 65536) 67 let entry: *u8 = sys_mmap(256); var ez: i64 = 0; while ez < 256 { entry[ez] = 0 as u8; ez = ez + 1 } 68 setu64(entry, 8, sysmem as i64) 69 let buf: *u8 = sys_mmap(512); var bz: i64 = 0; while bz < 512 { buf[bz] = 0 as u8; bz = bz + 1 } 70 setu32(buf, 0, device & 0xffffffff); setu64(buf, 32, desc as i64); setu32(buf, 40, 0) 71 setu32(buf, 44, 1); setu64(buf, 48, entry as i64); setu32(buf, 56, 0x10020) 72 let ret: i64 = sys_ioctl(fd, CALLOC_CODE, buf as i64); outh[0] = rd32(entry, 0); return ret 73} 74func map_va(fd: i64, pq: i64, alloc: i64, outva: *i64, outf: *i64) -> i64 { 75 let buf: *u8 = sys_mmap(256); var bz: i64 = 0; while bz < 256 { buf[bz] = 0 as u8; bz = bz + 1 } 76 setu32(buf, 0, pq & 0xffffffff); setu64(buf, 24, 0x10000000000) 77 setu32(buf, 32, alloc & 0xffffffff); setu64(buf, 48, 16); setu64(buf, 56, 1) 78 let ret: i64 = sys_ioctl(fd, MAPVA_CODE, buf as i64); outva[0] = rd64(buf, 88); outf[0] = rd64(buf, 96); return ret 79} 80func makeresident(fd: i64, pq: i64, alloc_handle: i64, outf: *i64) -> i64 { 81 let alist: *u8 = sys_mmap(64); setu32(alist, 0, alloc_handle & 0xffffffff) 82 let plist: *u8 = sys_mmap(64); setu32(plist, 0, 0) 83 let buf: *u8 = sys_mmap(256); var bz: i64 = 0; while bz < 256 { buf[bz] = 0 as u8; bz = bz + 1 } 84 setu32(buf, 0, pq & 0xffffffff); setu32(buf, 4, 1); setu64(buf, 8, alist as i64); setu64(buf, 16, plist as i64) 85 let ret: i64 = sys_ioctl(fd, MKRES_CODE, buf as i64); outf[0] = rd64(buf, 32); return ret 86} 87func wait_fence(fence_va: i64, target: i64) -> i64 { 88 let fpp: *i64 = fence_va as *i64; var iters: i64 = 0 89 while iters < 200000000 { if fpp[0] >= target { iters = 200000000 } else { iters = iters + 1 } } 90 return 0 91} 92 93func main() -> i64 { 94 p("=== SOVEREIGN-GPU R5a: Nishi-emitted pushbuffer -> the real 5080 writes a semaphore (read back CPU-side) ===\n" as *u8) 95 let fd: i64 = sys_openat_rd("/dev/dxg" as *u8) 96 if fd < 0 { p("open fail\n" as *u8); sys_exit(1); return 1 } 97 let ainfo: *u8 = sys_mmap(4096); var z: i64 = 0; while z < 4096 { ainfo[z] = 0 as u8; z = z + 1 } 98 let ereq: *u8 = sys_mmap(64); ereq[0] = 8 as u8; let r8: *i64 = (ereq as i64 + 8) as *i64; r8[0] = ainfo as i64 99 sys_ioctl(fd, ENUM2_CODE, ereq as i64); let nc: i64 = rd32(ereq, 0) 100 let v: *i64 = sys_mmap(16); var disc_lo: i64 = 0; var disc_hi: i64 = 0 101 var ai: i64 = 0 102 while ai < nc { 103 let base: i64 = ai * 20; let eh: i64 = rd32(ainfo, base) 104 let qret: i64 = query_type(fd, eh, 15, 4, v); let t: i64 = v[0] 105 if qret == 0 { if ((t>>4)&1) == 1 { if ((t>>2)&1) == 0 { disc_lo = rd32(ainfo, base+4); disc_hi = rd32(ainfo, base+8) } } } 106 ai = ai + 1 107 } 108 let ah: *i64 = sys_mmap(16); open_from_luid(fd, disc_lo, disc_hi, ah) 109 let dh: *i64 = sys_mmap(16); create_device(fd, ah[0], dh); let device: i64 = dh[0] 110 let ch: *i64 = sys_mmap(16); let cr: i64 = create_ctx(fd, device, ch); let context: i64 = ch[0] 111 let pqh: *i64 = sys_mmap(16); let fvah: *i64 = sys_mmap(16); create_pq(fd, device, pqh, fvah); let pq: i64 = pqh[0] 112 113 // pushbuffer (DMA) allocation + target allocation, both EXISTINGHEAP (CPU-backed), mapped + resident. 114 let sm_pb: *u8 = sys_mmap(65536); var a1: i64 = 0; while a1 < 65536 { sm_pb[a1] = 0 as u8; a1 = a1 + 1 } 115 let sm_tg: *u8 = sys_mmap(65536); var a2: i64 = 0; while a2 < 65536 { sm_tg[a2] = 0 as u8; a2 = a2 + 1 } 116 let pbh: *i64 = sys_mmap(16); alloc_eh(fd, device, sm_pb, pbh); let pb_alloc: i64 = pbh[0] 117 let tgh: *i64 = sys_mmap(16); alloc_eh(fd, device, sm_tg, tgh); let tg_alloc: i64 = tgh[0] 118 let pbva: *i64 = sys_mmap(16); let dummy1: *i64 = sys_mmap(16); map_va(fd, pq, pb_alloc, pbva, dummy1); let pb_va: i64 = pbva[0] 119 let tgva: *i64 = sys_mmap(16); let dummy2: *i64 = sys_mmap(16); map_va(fd, pq, tg_alloc, tgva, dummy2); let tg_va: i64 = tgva[0] 120 let mf1: *i64 = sys_mmap(16); makeresident(fd, pq, pb_alloc, mf1) 121 let mf2: *i64 = sys_mmap(16); makeresident(fd, pq, tg_alloc, mf2) 122 p(" context=" as *u8); x(context); p(" pb_va=" as *u8); x(pb_va); p(" tg_va=" as *u8); x(tg_va); p("\n" as *u8) 123 124 // SOVEREIGN EMIT: write the 6-dword semaphore-release pushbuffer into the pushbuffer's CPU-backed memory. 125 let PAYLOAD: i64 = 0xCAFEBABE 126 setu32(sm_pb, 0, 0x20050017) // header: increasing, count=5, subch0, method 0x5c>>2 127 setu32(sm_pb, 4, tg_va & 0xffffffff) // SEM_ADDR_LO 128 setu32(sm_pb, 8, (tg_va >> 32) & 0xffffffff) // SEM_ADDR_HI 129 setu32(sm_pb, 12, PAYLOAD) // SEM_PAYLOAD_LO 130 setu32(sm_pb, 16, 0) // SEM_PAYLOAD_HI 131 setu32(sm_pb, 20, 0x1) // SEM_EXECUTE: OPERATION_RELEASE, 32-bit 132 p(" emitted pushbuffer[0..6]=" as *u8); x(rd32(sm_pb,0)); p(" " as *u8); x(rd32(sm_pb,4)); p(" " as *u8); x(rd32(sm_pb,8)); p(" " as *u8); x(rd32(sm_pb,12)); p(" " as *u8); x(rd32(sm_pb,16)); p(" " as *u8); x(rd32(sm_pb,20)); p("\n" as *u8) 133 134 // SUBMIT (size 384): command_buffer@0 = pushbuffer GPU VA, command_length@8 = 24, count@0x18 = 1, ctx[0]@0x20. 135 let sb: *u8 = sys_mmap(1024); var sz: i64 = 0; while sz < 1024 { sb[sz] = 0 as u8; sz = sz + 1 } 136 setu64(sb, 0, pb_va); setu32(sb, 8, 24); setu32(sb, 0x18, 1); setu32(sb, 0x1c, context & 0xffffffff) // broadcast_context[0]@0x1c (probe-confirmed) 137 let sr: i64 = sys_ioctl(fd, SUBMIT_CODE, sb as i64) 138 p(" SUBMITCOMMAND ret=" as *u8); n(sr); p("\n" as *u8) 139 140 // wait for the GPU to write the semaphore, then read the target CPU-side. 141 wait_fence(fvah[0], mf2[0]) 142 let tgt_word: *i64 = sm_tg as i64 as *i64 143 var iters: i64 = 0; var got: i64 = 0 144 while iters < 300000000 { let w: i64 = rd32(sm_tg, 0); if w == PAYLOAD { got = w; iters = 300000000 } else { iters = iters + 1 } } 145 let final: i64 = rd32(sm_tg, 0) 146 p(" target buffer (CPU read) = " as *u8); x(final); p(" expected=" as *u8); x(PAYLOAD); p("\n" as *u8) 147 if final == PAYLOAD { p(" *** THE RTX 5080 EXECUTED OUR SOVEREIGN PUSHBUFFER (semaphore written) ***\n" as *u8) } 148 else { p(" (semaphore not observed -- submit ret + value above; iterate on context-engine/pushbuffer/coherency)\n" as *u8) } 149 sys_close(fd) 150 p("=== R5a DONE ===\n" as *u8) 151 return 0 152}