code wiki / _hdl_build / _gpu_dxg_alloc_gate.nx

_gpu_dxg_alloc_gate.nx

buildroot/runtime/_hdl_build/_gpu_dxg_alloc_gate.nx

11275 B141 linesdepth 2pulls 2 transitivereach 0 importersview sourcekind gate/prooftopic gpu
docsdependenciesstructsconstsfunctions

about

_gpu_dxg_alloc_gate.nx -- SOVEREIGN-GPU ladder R4d (allocate REAL GPU memory on the 5080, UMD-less). R4c built the paging queue. R4d allocates actual memory through LX_DXCREATEALLOCATION via the UMD-less STANDARD-ALLOCATION / EXISTINGHEAP path -- no vendor (NVIDIA) UMD blob needed. The recipe was reverse- engineered: fault-probes pinned device@0/alloc_count@44/allocation_info@48; the WSL2-Linux-Kernel header (WebFetch, verified vs runtime) gave the field layout; and dxgkio_create_allocation's open-source validation gave the exact requirements: flags@56 = standard_allocation(bit16,0x10000) | existing_sysmem(bit5,0x20) = 0x10020 priv_drv_data_size@40 = 0 ; alloc_count@44 = 1 standard_allocation@32 -> d3dkmt_createstandardallocation{ type@0=EXISTINGHEAP(1); existing_heap.size@8 (!=0, page-aligned) } allocation_info@48 -> d3dddi_allocationinfo2{ sysmem@8 (!=NULL, page-aligned); allocation@0 (OUT handle); gpu_virtual_address@40 (OUT) } GREEN iff (author=organ, from REAL device returns): A) device-create chain ok; B) CREATEALLOCATION #1 ret==0 AND allocation handle != 0 (written into pre-zeroed entry@0); C) CREATEALLOCATION #2 (distinct sysmem) ret==0 AND handle != 0 AND != #1 (per-call REAL allocation, not a constant); D) TAMPER matrix, each from a real validation rule, all != the real ret==0: T1 flags w/o existing_sysmem (0x10000) -> STATUS_INVALID_PARAMETER; T2 priv_drv_data_size=16 -> -EINVAL; T3 existing_heap.size unaligned (65535) -> -EINVAL; T4 on a non-dxg fd -> -ENOTTY. fd close frees the allocations (per-fd dxgkrnl cleanup). Marker -> knowledge/status/gpu_dxg.log (DXGALLOCGATE). raw syscalls only. NO-WAVE: allocates memory (a real GPU object); gpu_va mapping=R4e, compute/throughput=R7. ZERO throughput. license_tier: ORIGINAL

dependencies 1 imports · 0 importers

nx_syscalls.nx _gpu_dxg_alloc_gate.nx

imports: nx_syscalls.nx

imported by: nobody (leaf or entry point)

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

main p sys_write sys_openat_rd sys_exit sys_mmap sys_ioctl rd32 query_type sys_mmap ↻ sys_ioctl ↻ rd32 ↻ open_from_luid sys_mmap ↻ sys_ioctl ↻ rd32 ↻ create_device sys_mmap ↻ setu32 sys_ioctl ↻ rd32 ↻ n sys_mmap ↻ sys_write ↻ x p ↻ sys_mmap ↻ sys_write ↻ alloc_eh sys_mmap ↻ setu32 ↻ setu64 sys_ioctl ↻ rd32 ↻ rd64 sys_close sys_openat_append fp sys_write ↻ fx

structs

none

consts

25const ENUM2_CODE: i64 = 0xC0104714
26const QAI_CODE: i64 = 0xC0184709
27const OAFL_CODE: i64 = 0xC00C4701
28const CDEV_CODE: i64 = 0xC0404702
29const CALLOC_CODE: i64 = 0xC0484706

functions

31func p(s: *u8) -> i64 { var nn: i64=0; while s[nn]!=(0 as u8){nn=nn+1} sys_write(1,s,nn); return 0 }
called by 2: xmain calls 1: sys_write
32func fp(fd: i64, s: *u8) -> i64 { var nn: i64=0; while s[nn]!=(0 as u8){nn=nn+1} sys_write(fd,s,nn); return 0 }
called by 2: fxmain calls 1: sys_write
33func n(v: i64) -> i64 { let bb: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m;sys_write(1,"-" as *u8,1)}; let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48;k=1}; while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1}; var i: i64=0; while i<k{bb[i]=t[k-1-i];i=i+1}; sys_write(1,bb,k); return 0 }
called by 1: main calls 2: sys_mmapsys_write
34func x(v: i64) -> i64 { p("0x" as *u8); let bb:*u8=sys_mmap(20); var k:i64=0; var m:i64=v; if m==0{bb[0]=48;k=1}; while m>0{ let d:i64=m&15; if d<10{bb[k]=(48+d) as u8}else{bb[k]=(87+d) as u8}; m=(m>>4); k=k+1 } var i:i64=0; let o:*u8=sys_mmap(20); while i<k{o[i]=bb[k-1-i];i=i+1} sys_write(1,o,k); return 0 }
called by 1: main calls 3: psys_mmapsys_write
35func fx(fd: i64, v: i64) -> i64 { let bb:*u8=sys_mmap(20); var k:i64=0; var m:i64=v; if m==0{bb[0]=48;k=1}; while m>0{ let d:i64=m&15; if d<10{bb[k]=(48+d) as u8}else{bb[k]=(87+d) as u8}; m=(m>>4); k=k+1 } let o:*u8=sys_mmap(20); var i:i64=0; while i<k{o[i]=bb[k-1-i];i=i+1} fp(fd,"0x" as *u8); sys_write(fd,o,k); return 0 }
called by 1: main calls 3: sys_mmapfpsys_write
36func rd32(buf: *u8, off: i64) -> i64 { return (buf[off] as i64)|((buf[off+1] as i64)<<8)|((buf[off+2] as i64)<<16)|((buf[off+3] as i64)<<24) }
37func rd64(buf: *u8, off: i64) -> i64 { let q: *i64 = (buf as i64 + off) as *i64; return q[0] }
called by 1: alloc_eh
38func setu32(buf: *u8, off: i64, val: i64) -> i64 { let w: *u8 = (buf as i64 + off) as *u8; w[0]=(val&0xff) as u8; w[1]=((val>>8)&0xff) as u8; w[2]=((val>>16)&0xff) as u8; w[3]=((val>>24)&0xff) as u8; return 0 }
39func setu64(buf: *u8, off: i64, val: i64) -> i64 { let q: *i64 = (buf as i64 + off) as *i64; q[0]=val; return 0 }
called by 1: alloc_eh
41func query_type(fd: i64, handle: i64, qtype: i64, psize: i64, outv: *i64) -> i64
called by 1: main calls 3: sys_mmapsys_ioctlrd32
49func open_from_luid(fd: i64, luid_lo: i64, luid_hi: i64, outh: *i64) -> i64
called by 1: main calls 3: sys_mmapsys_ioctlrd32
54func create_device(fd: i64, adapter: i64, outd: *i64) -> i64
called by 1: main calls 4: sys_mmapsetu32sys_ioctlrd32
60func alloc_eh(fd: i64, device: i64, sysmem: *u8, heapsize: i64, flags: i64, priv_size: i64, outh: *i64, outva: *i64) -> i64
74func main() -> i64