code wiki / _hdl_build / _gpu_dxg_gate.nx

_gpu_dxg_gate.nx

buildroot/runtime/_hdl_build/_gpu_dxg_gate.nx

7258 B98 linesdepth 3pulls 3 transitivereach 0 importersview sourcekind gate/prooftopic gpu
docsdependenciesstructsconstsfunctions

about

_gpu_dxg_gate.nx -- GATE for the SOVEREIGN-GPU foundation rung (R0): proves Nishi reaches the REAL RTX 5080 through /dev/dxg (the WSL dxgkrnl last-mile) with RAW syscalls only -- the emitted elf links NOTHING (no libvulkan / libcuda / libdxcore / libd3d12 / libc). The verdict comes from a REAL ioctl to the REAL device returning REAL adapter data (count + non-zero LUID), NOT from $?. AUTHOR=ORGAN / NO-FALSE-GREEN -- the gate runs the real nx_gpu_dxg_probe mechanism three ways against the SAME binary and asserts ALL must hold: (A) REAL CALL on /dev/dxg: LX_DXENUMADAPTERS2 ret==0 AND num_adapters>=1 AND a non-zero adapter[0] LUID/handle came back from the 5080. (B) TAMPER (magic-0x99 ioctl on the SAME real /dev/dxg fd): the device rejects it with a real errno (< 0, observed -25 ENOTTY) that DIFFERS from the real ret==0. A 0 here = the fd is a no-op => RED. This proves ret==0 is a real device ACCEPT, not "any ioctl returns 0". (C) NON-DXG FD control (/dev/null): the EXACT SAME LX_DXENUMADAPTERS2 ioctl returns a real errno (< 0, ENOTTY) -- NOT 0 and NOT adapter data. This proves the green depends on the REAL dxgkrnl device behind /dev/dxg, not on merely having an open fd. GREEN iff (A) AND (B) AND (C). Any failure -> RED with the real returned values, NEVER a fake green. SCOPE (NO-WAVE): GREEN here means ONLY "Nishi reaches the real RTX 5080 sovereignly via the /dev/dxg paravirt last-mile". It claims NO throughput / speedup / exceed (that is R7, a real cuBLAS head-to-head many rungs up). This is the FOUNDATION rung the GPU ladder rests on. SELF-CONTAINED: imports nx_gpu_dxg_probe and calls dxg_enumadapters() in-process -- it does NOT fork a prebuilt _offc/*.elf, so the /tmp->_offc install landmine does not apply to this gate. Evidence -> knowledge/status/gpu_dxg.log. license_tier: ORIGINAL

dependencies 2 imports · 0 importers

nx_syscalls.nx nx_gpu_dxg_probe.nx _gpu_dxg_gate.nx

imports: nx_syscalls.nxnx_gpu_dxg_probe.nx

imported by: nobody (leaf or entry point)

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

main g_p sys_write sys_openat_append sys_mmap dxg_enumadapters sys_openat_rd dxr_set sys_mmap ↻ sys_ioctl sys_close dxr_get g_fn sys_mmap ↻ sys_write ↻ g_x g_p ↻ sys_mmap ↻ sys_write ↻ g_fp sys_write ↻ g_fx g_fp ↻ sys_mmap ↻ sys_write ↻ sys_now_realtime_sec sys_mmap ↻ sys_clock_gettime_real sys_close ↻ sys_exit

structs

none

consts

none

functions

28func g_p(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 }
called by 2: g_xmain calls 1: sys_write
29func g_x(v: i64) -> i64 { g_p("0x" as *u8); let bb:*u8=sys_mmap(20); var k:i64=0; var m:i64=v; if m==0{bb[0]=48;k=1}; while m>0{ let d:i64=m&15; if d<10{bb[k]=(48+d) as u8}else{bb[k]=(87+d) as u8}; m=(m>>4); k=k+1 } var i:i64=0; let o:*u8=sys_mmap(20); while i<k{o[i]=bb[k-1-i];i=i+1} sys_write(1,o,k); return 0 }
called by 1: main calls 3: g_psys_mmapsys_write
30func g_fp(fd: i64, s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(fd,s,n); return 0 }
called by 2: g_fxmain calls 1: sys_write
31func g_fn(fd: i64, v: i64) -> i64 { let bb: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m;sys_write(fd,"-" as *u8,1)}; let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48;k=1}; while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1}; var i: i64=0; while i<k{bb[i]=t[k-1-i];i=i+1}; sys_write(fd,bb,k); return 0 }
called by 1: main calls 2: sys_mmapsys_write
32func g_fx(fd: i64, v: i64) -> i64 { g_fp(fd,"0x" as *u8); let bb:*u8=sys_mmap(20); var k:i64=0; var m:i64=v; if m==0{bb[0]=48;k=1}; while m>0{ let d:i64=m&15; if d<10{bb[k]=(48+d) as u8}else{bb[k]=(87+d) as u8}; m=(m>>4); k=k+1 } var i:i64=0; let o:*u8=sys_mmap(20); while i<k{o[i]=bb[k-1-i];i=i+1} sys_write(fd,o,k); return 0 }
called by 1: main calls 3: g_fpsys_mmapsys_write
34func main() -> i64