_gpu_bm_gpfifo_gate.nx

_gpu_bm_gpfifo_gate.nx -- BARE-METAL SOVEREIGN-GPU rung BM-GPU-1: a spec-accurate sovereign NVIDIA GPFIFO MODEL executes the SAME pushbuffer our emitter produces -> the semaphore payload lands in modeled GPU memory. WHY: WSL GPU-PV gatekeeps execution (host translates the cmd buffer; raw pushbuffers ignored -- R5a payload- independence test). The TRUE hardware-rung-up sovereign path is bare-metal (native Linux + PCIe/BAR0/doorbell). This rung builds the development substrate + closes the loop WSL broke: a faithful model of the NVIDIA host/FIFO (GF100 method-header decode + NVC56F semaphore-release semantics, straight from the open hardware spec) that EXECUTES our sovereign pushbuffer. NISHI-ECOSYSTEM-ONLY: our model + our driver + our pushbuffer; the NVIDIA command format is the last-mile hardware protocol (the benchmark to drive real iron), emitted+interpreted by us. HONEST SCOPE: this verifies the command-emission + FIFO-execution LOGIC against a spec-accurate model (the same way the driver-from-spec arc gates against gold device models). It does NOT execute on the real 5080 -- that is the bare-metal PCIe/doorbell last-mile (when on native Linux owning the GPU). NO real silicon, NO throughput. GREEN iff (author=organ): our emitted pushbuffer, run through the SPEC-FAITHFUL GPFIFO model, writes the exact payload to the exact semaphore address; AND tampers (corrupt method offset / non-RELEASE op / short count) all FAIL to write -> the model is faithful, so a real NVIDIA FIFO would behave identically. Marker -> knowledge/status/gpu_baremetal.log (BMGPFIFOGATE). license_tier: ORIGINAL