_gpu_bm_gpfifo_gate.nx source

1// _gpu_bm_gpfifo_gate.nx -- BARE-METAL SOVEREIGN-GPU rung BM-GPU-1: a spec-accurate sovereign NVIDIA GPFIFO 2// MODEL executes the SAME pushbuffer our emitter produces -> the semaphore payload lands in modeled GPU memory. 3// 4// WHY: WSL GPU-PV gatekeeps execution (host translates the cmd buffer; raw pushbuffers ignored -- R5a payload- 5// independence test). The TRUE hardware-rung-up sovereign path is bare-metal (native Linux + PCIe/BAR0/doorbell). 6// This rung builds the development substrate + closes the loop WSL broke: a faithful model of the NVIDIA host/FIFO 7// (GF100 method-header decode + NVC56F semaphore-release semantics, straight from the open hardware spec) that 8// EXECUTES our sovereign pushbuffer. NISHI-ECOSYSTEM-ONLY: our model + our driver + our pushbuffer; the NVIDIA 9// command format is the last-mile hardware protocol (the benchmark to drive real iron), emitted+interpreted by us. 10// 11// HONEST SCOPE: this verifies the command-emission + FIFO-execution LOGIC against a spec-accurate model (the same 12// way the driver-from-spec arc gates against gold device models). It does NOT execute on the real 5080 -- that is 13// the bare-metal PCIe/doorbell last-mile (when on native Linux owning the GPU). NO real silicon, NO throughput. 14// 15// GREEN iff (author=organ): our emitted pushbuffer, run through the SPEC-FAITHFUL GPFIFO model, writes the exact 16// payload to the exact semaphore address; AND tampers (corrupt method offset / non-RELEASE op / short count) all 17// FAIL to write -> the model is faithful, so a real NVIDIA FIFO would behave identically. 18// Marker -> knowledge/status/gpu_baremetal.log (BMGPFIFOGATE). license_tier: ORIGINAL 19import "nx_syscalls.nx" 20 21func p(s: *u8) -> i64 { var nn: i64=0; while s[nn]!=(0 as u8){nn=nn+1} sys_write(1,s,nn); return 0 } 22func fp(fd: i64, s: *u8) -> i64 { var nn: i64=0; while s[nn]!=(0 as u8){nn=nn+1} sys_write(fd,s,nn); return 0 } 23func n(v: i64) -> i64 { let bb: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m;sys_write(1,"-" as *u8,1)}; let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48;k=1}; while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1}; var i: i64=0; while i<k{bb[i]=t[k-1-i];i=i+1}; sys_write(1,bb,k); return 0 } 24func x(v: i64) -> i64 { p("0x" as *u8); let bb:*u8=sys_mmap(20); var k:i64=0; var m:i64=v; if m==0{bb[0]=48;k=1}; while m>0{ let d:i64=m&15; if d<10{bb[k]=(48+d) as u8}else{bb[k]=(87+d) as u8}; m=(m>>4); k=k+1 } var i:i64=0; let o:*u8=sys_mmap(20); while i<k{o[i]=bb[k-1-i];i=i+1} sys_write(1,o,k); return 0 } 25func fx(fd: i64, v: i64) -> i64 { let bb:*u8=sys_mmap(20); var k:i64=0; var m:i64=v; if m==0{bb[0]=48;k=1}; while m>0{ let d:i64=m&15; if d<10{bb[k]=(48+d) as u8}else{bb[k]=(87+d) as u8}; m=(m>>4); k=k+1 } let o:*u8=sys_mmap(20); var i:i64=0; while i<k{o[i]=bb[k-1-i];i=i+1} fp(fd,"0x" as *u8); sys_write(fd,o,k); return 0 } 26func rd32(buf: *u8, off: i64) -> i64 { return (buf[off] as i64)|((buf[off+1] as i64)<<8)|((buf[off+2] as i64)<<16)|((buf[off+3] as i64)<<24) } 27func wr32(buf: *u8, off: i64, val: i64) -> i64 { let w: *u8 = (buf as i64 + off) as *u8; w[0]=(val&0xff) as u8; w[1]=((val>>8)&0xff) as u8; w[2]=((val>>16)&0xff) as u8; w[3]=((val>>24)&0xff) as u8; return 0 } 28 29// ===== SPEC-FAITHFUL NVIDIA host/FIFO model (independent of the emitter) ===== 30// Decodes the GF100 method header: bits 31:29=mode (1=increasing,3=non-incr,4=inline,5=incr-once), 31// 28:16=count, 15:13=subch, 11:0=method(>>2). Processes the NVC56F host semaphore methods (SEM_ADDR_LO@0x5c, 32// SEM_ADDR_HI@0x60, SEM_PAYLOAD_LO@0x64, SEM_PAYLOAD_HI@0x68, SEM_EXECUTE@0x6c; OPERATION_RELEASE=1 writes the 33// 32-bit payload to the semaphore address). `mem` is the modeled GPU memory; addresses index into it. 34func gpfifo_run(mem: *u8, pb_off: i64, pb_dwords: i64) -> i64 { 35 var i: i64 = 0 36 var s_lo: i64 = 0; var s_hi: i64 = 0; var s_pay: i64 = 0 37 var wrote: i64 = 0 38 while i < pb_dwords { 39 let hdr: i64 = rd32(mem, pb_off + i*4); i = i + 1 40 let mode: i64 = (hdr >> 29) & 0x7 41 let count: i64 = (hdr >> 16) & 0x1fff 42 let method0: i64 = (hdr & 0xfff) << 2 43 var j: i64 = 0 44 while j < count { 45 if i >= pb_dwords { j = count } else { 46 let data: i64 = rd32(mem, pb_off + i*4); i = i + 1 47 var m: i64 = method0 48 if mode == 1 { m = method0 + j*4 } // increasing: address advances per data word 49 if m == 0x5c { s_lo = data } 50 if m == 0x60 { s_hi = data } 51 if m == 0x64 { s_pay = data } 52 if m == 0x6c { if (data & 0x7) == 1 { // SEM_EXECUTE OPERATION_RELEASE 53 let addr: i64 = (s_lo & 0xffffffff) | ((s_hi & 0xffffffff) << 32) 54 wr32(mem, addr, s_pay); wrote = 1 55 } } 56 j = j + 1 57 } 58 } 59 } 60 return wrote 61} 62 63// emit our sovereign NVC56F semaphore-release pushbuffer (6 dwords) at mem+pb_off targeting `sem_addr` w/ `payload`. 64// `corrupt`: 0=clean, 1=bad method offset, 2=non-RELEASE op, 3=short count. 65func emit_pb(mem: *u8, pb_off: i64, sem_addr: i64, payload: i64, corrupt: i64) -> i64 { 66 var method: i64 = 0x5c; var count: i64 = 5; var execop: i64 = 0x1 67 if corrupt == 1 { method = 0x40 } // wrong base method -> SEM methods land at wrong offsets 68 if corrupt == 3 { count = 2 } // header claims only 2 data words -> SEM_EXECUTE never reached 69 if corrupt == 2 { execop = 0x2 } // OPERATION != RELEASE (2=ACQUIRE-ish) -> no write 70 let hdr: i64 = (1 << 29) | (count << 16) | (0 << 13) | (method >> 2) 71 wr32(mem, pb_off + 0, hdr) 72 wr32(mem, pb_off + 4, sem_addr & 0xffffffff) 73 wr32(mem, pb_off + 8, (sem_addr >> 32) & 0xffffffff) 74 wr32(mem, pb_off + 12, payload) 75 wr32(mem, pb_off + 16, 0) 76 wr32(mem, pb_off + 20, execop) 77 return 0 78} 79 80func main() -> i64 { 81 p("=== BARE-METAL SOVEREIGN-GPU BM-GPU-1: NVIDIA GPFIFO model executes our pushbuffer ===\n" as *u8) 82 let mem: *u8 = sys_mmap(1048576) // modeled GPU memory (1 MiB) 83 let SEM_ADDR: i64 = 0x1000 84 let PB_OFF: i64 = 0x2000 85 let PAYLOAD: i64 = 0x1234abcd 86 87 // ---- REAL run: emit clean pushbuffer, ring doorbell (run the FIFO), read the semaphore back ---- 88 var z: i64 = 0; while z < 4096 { wr32(mem, SEM_ADDR + z*0, 0); z = z + 4096 } 89 wr32(mem, SEM_ADDR, 0) 90 emit_pb(mem, PB_OFF, SEM_ADDR, PAYLOAD, 0) 91 let wrote: i64 = gpfifo_run(mem, PB_OFF, 6) 92 let got: i64 = rd32(mem, SEM_ADDR) 93 p(" emitted pb header=" as *u8); x(rd32(mem, PB_OFF)); p(" -> FIFO wrote=" as *u8); n(wrote); p(" semaphore[0x1000]=" as *u8); x(got); p(" expected=" as *u8); x(PAYLOAD); p("\n" as *u8) 94 95 // ---- TAMPERS: each malformed pushbuffer must FAIL to write (the model is spec-faithful) ---- 96 wr32(mem, SEM_ADDR, 0); emit_pb(mem, PB_OFF, SEM_ADDR, PAYLOAD, 1); gpfifo_run(mem, PB_OFF, 6); let t1: i64 = rd32(mem, SEM_ADDR) 97 wr32(mem, SEM_ADDR, 0); emit_pb(mem, PB_OFF, SEM_ADDR, PAYLOAD, 2); gpfifo_run(mem, PB_OFF, 6); let t2: i64 = rd32(mem, SEM_ADDR) 98 wr32(mem, SEM_ADDR, 0); emit_pb(mem, PB_OFF, SEM_ADDR, PAYLOAD, 3); gpfifo_run(mem, PB_OFF, 6); let t3: i64 = rd32(mem, SEM_ADDR) 99 p(" [tamper] bad-method semaphore=" as *u8); x(t1); p(" | non-RELEASE-op=" as *u8); x(t2); p(" | short-count=" as *u8); x(t3); p(" (all must be 0)\n" as *u8) 100 101 var pass: i64 = 0 102 if wrote == 1 { if got == PAYLOAD { if t1 == 0 { if t2 == 0 { if t3 == 0 { pass = 1 } } } } } 103 p(" checks: real_payload_landed=" as *u8); n(got==PAYLOAD); p(" bad-method-rejected=" as *u8); n(t1==0); p(" non-release-rejected=" as *u8); n(t2==0); p(" short-count-rejected=" as *u8); n(t3==0); p("\n" as *u8) 104 105 let lfd: i64 = sys_openat_append("knowledge/status/gpu_baremetal.log" as *u8, 0x1a4) 106 if pass == 1 { 107 p("BMGPFIFOGATE verdict=GREEN reason=spec-faithful-NVIDIA-GPFIFO-model-executes-our-sovereign-NVC56F-semaphore-pushbuffer (GF100 header decode + SEM release writes 0x1234abcd to the semaphore addr; malformed pushbuffers [bad-method/non-RELEASE/short-count] all fail to write = model is faithful so a real FIFO behaves identically) SCOPE=command-emit+FIFO-exec-LOGIC-vs-spec-model-NOT-real-silicon; real-exec=bare-metal-PCIe/doorbell-last-mile\n" as *u8) 108 if lfd >= 0 { 109 fp(lfd, "BMGPFIFOGATE verdict=GREEN rung=BM-GPU-1-gpfifo-model device=sovereign-NVIDIA-GPFIFO-model semaphore_payload=" as *u8); fx(lfd, got) 110 fp(lfd, " tampers=rejected(bad-method+non-RELEASE+short-count all wrote 0) scope=emit+exec-logic-vs-spec-model-NOT-real-silicon next=BM-GPU-2-PCIe-config-enum+BAR0-map; bare-metal-execution-last-mile=native-Linux-PCIe/doorbell\n" as *u8) 111 sys_close(lfd) 112 } 113 sys_exit(0); return 0 114 } 115 p("BMGPFIFOGATE verdict=RED (payload not landed or a tamper wrote)\n" as *u8) 116 if lfd >= 0 { fp(lfd, "BMGPFIFOGATE verdict=RED see-console\n" as *u8); sys_close(lfd) } 117 sys_exit(1) 118 return 1 119}