_gpu_bm_qmd_v5_gate.nx

_gpu_bm_qmd_v5_gate.nx -- BARE-METAL SOVEREIGN-GPU rung BM-GPU-7a: REAL Blackwell QMDV05_00 descriptor. Hardens BM-GPU-C2 (_gpu_bm_qmd_gate): that rung's LAUNCH METHODS were faithful (SET_OBJECT 0xCDC0 + SEND_PCAS_A 0x2b4 + SEND_SIGNALING_PCAS2_B 0x2c0 + PCAS_ACTION=SCHEDULE) but its QMD-INTERNAL field offsets were REPRESENTATIVE ("QMDV0x bit-packing wasn't locatable"). THIS rung writes the REAL QMDV05_00 bit-packed layout, recovered (deep-research, 3-0 verified) verbatim from NVIDIA's open header classes/compute/clcdc0qmd.h and independently mirrored in tinygrad's NVCEC0_QMDV05_00. So the GPU LAUNCH DESCRIPTOR is now byte/bit-FAITHFUL to NVIDIA's published Blackwell spec, not a stand-in. QMDV05_00 fields are MW(hi:lo) BIT ranges over a 3072-bit (384-byte) struct (NOT plain byte fields): PROGRAM_ADDRESS_LOWER_SHIFTED4 MW(1055:1024), UPPER_SHIFTED4 MW(1076:1056) [stored = addr>>4] CTA_THREAD_DIMENSION0/1/2 MW(1103:1088)/(1119:1104)/(1127:1120) [block dims] CTA_RASTER_WIDTH/HEIGHT/DEPTH MW(1279:1248)/(1295:1280)/(1327:1312) [grid dims] REGISTER_COUNT MW(1136:1128); SHARED_MEMORY_SIZE_SHIFTED7 MW(1162:1152) CONSTANT_BUFFER_ADDR_LOWER_SHIFTED6(i) MW((1375+i*64):(1344+i*64)), UPPER_SHIFTED6(i) MW((1394+i*64):(1376+i*64)) CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1407+i*64):(1395+i*64)); VALID(i) MW((1856+i*4):(1856+i*4)) QMD_GROUP_ID MW(149:144) HONEST SCOPE (no-false-green): the QMD LAYOUT is now REAL (round-trip: every field written at its real bit range reads back exactly; the SKED extracts program_address + the const-buffer VA from the REAL offsets and the GEMM runs off that real cbuf pointer). The SASS kernel itself STILL STANDS IN -- real Blackwell sm_120 SASS is not hand-emittable from open sources yet (encoding/control-bits unsolved; only Mesa NAK can emit it) = BM-GPU-7b, blocked on the open ecosystem / real silicon. So: descriptor REAL, machine-code modeled. GREEN iff: A) all real QMDV05_00 fields round-trip (write->read at real bit offsets == value); B) the SKED reading program_address + cbuf from the REAL offsets dispatches a GEMM == independent reference; C) TAMPER: zeroing CONSTANT_BUFFER_VALID(0) OR a wrong bit range -> field/dispatch mismatch (the real layout is load-bearing). Marker -> knowledge/status/gpu_baremetal.log (BMQMDV5GATE). license_tier: ORIGINAL