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_gpu_bm_gmmu_gate.nx
buildroot/runtime/_hdl_build/_gpu_bm_gmmu_gate.nx
about
_gpu_bm_gmmu_gate.nx -- BARE-METAL SOVEREIGN-GPU rung BM-GPU-MMU: the NVIDIA GMMU (GPU page tables) VA->PA
translation -- FULLY FAITHFUL (no stand-in: pure deterministic address translation).
Hardens the implicit "GPU VA = direct offset" simplification in every model rung with a real GMMU. Sovereign
driver builds GP100+ (Pascal..Blackwell) page tables; a faithful 5-level radix walker translates VA->PA.
PTE format (from nouveau gp100_vmm_pgt_pte): VALID@0, APERTURE@2:1 (VRAM=1), VOL@3, PRIV@5, RO@6; physical addr =
(PA>>4) merged into the upper bits (4KB-aligned PA -> low 8 bits free for the flags). Decode PA=(PTE&~0xFF)<<4.
5-level radix for 49-bit VAs: index bits per level {2,9,9,8,9}, 12-bit page offset. PDE = (next_table>>4)|valid|aperture.
NISHI-ECOSYSTEM-ONLY: our model+driver; GMMU format = last-mile hardware spec (VERIFIED vs nouveau). This rung is
FAITHFUL end-to-end (real format + real bit-splits + real walk); it transfers to real silicon at BM-GPU-6.
GREEN iff: map VA1->PA1, VA2->PA2 then translate -> exact PA+page-offset; an UNMAPPED VA FAULTS; a corrupted
(valid-cleared) PTE FAULTS; a read-only mapping decodes its RO bit.
Marker -> knowledge/status/gpu_baremetal.log (BMMMUGATE). license_tier: ORIGINAL
dependencies 1 imports · 0 importers
imports: nx_syscalls.nx
imported by: nobody (leaf or entry point)
call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown
structs
| none |
consts
| 25 | const APERTURE_VRAM: i64 = 2 // (1 << 1): aperture field = VRAM |
| 26 | const PTE_VALID: i64 = 1 |
| 27 | const PTE_RO: i64 = 0x40 // bit 6 |
functions
| 17 | func p(s: *u8) -> i64 { var nn: i64=0; while s[nn]!=(0 as u8){nn=nn+1} sys_write(1,s,nn); return 0 } |
| 18 | func fp(fd: i64, s: *u8) -> i64 { var nn: i64=0; while s[nn]!=(0 as u8){nn=nn+1} sys_write(fd,s,nn); return 0 } |
| 19 | func n(v: i64) -> i64 { let bb: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m;sys_write(1,"-" as *u8,1)}; let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48;k=1}; while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1}; var i: i64=0; while i<k{bb[i]=t[k-1-i];i=i+1}; sys_write(1,bb,k); return 0 } |
| 20 | func x(v: i64) -> i64 { p("0x" as *u8); let bb:*u8=sys_mmap(20); var k:i64=0; var m:i64=v; if m==0{bb[0]=48;k=1}; while m>0{ let d:i64=m&15; if d<10{bb[k]=(48+d) as u8}else{bb[k]=(87+d) as u8}; m=(m>>4); k=k+1 } var i:i64=0; let o:*u8=sys_mmap(20); while i<k{o[i]=bb[k-1-i];i=i+1} sys_write(1,o,k); return 0 } |
| 21 | func fx(fd: i64, v: i64) -> i64 { let bb:*u8=sys_mmap(20); var k:i64=0; var m:i64=v; if m==0{bb[0]=48;k=1}; while m>0{ let d:i64=m&15; if d<10{bb[k]=(48+d) as u8}else{bb[k]=(87+d) as u8}; m=(m>>4); k=k+1 } let o:*u8=sys_mmap(20); var i:i64=0; while i<k{o[i]=bb[k-1-i];i=i+1} fp(fd,"0x" as *u8); sys_write(fd,o,k); return 0 } |
| 22 | func rd64(b: *u8, o: i64) -> i64 { let q: *i64 = (b as i64 + o) as *i64; return q[0] } |
| 23 | func wr64(b: *u8, o: i64, v: i64) -> i64 { let q: *i64 = (b as i64 + o) as *i64; q[0] = v; return 0 } |
| 30 | func pt_alloc(gmem: *u8, st: *i64) -> i64 |
| 36 | func lvl_shift(l: i64) -> i64 { if l==0 { return 47 } if l==1 { return 38 } if l==2 { return 29 } if l==3 { return 21 } return 12 } |
| 37 | func lvl_bits(l: i64) -> i64 { if l==0 { return 2 } if l==1 { return 9 } if l==2 { return 9 } if l==3 { return 8 } return 9 } |
| 40 | func pt_map(gmem: *u8, st: *i64, root: i64, va: i64, pa: i64, ro: i64) -> i64 |
| 59 | func pt_translate(gmem: *u8, root: i64, va: i64, out: *i64) -> i64 |
| 75 | func main() -> i64 |