code wiki / _hdl_build / _gpu_compute_gate.nx

_gpu_compute_gate.nx

buildroot/runtime/_hdl_build/_gpu_compute_gate.nx

10537 B188 linesdepth 2pulls 2 transitivereach 0 importersview sourcekind gate/prooftopic gpu
docsdependenciesstructsconstsfunctions

about

_gpu_compute_gate.nx -- GPU-COMPUTE bit-identical CPU-vs-GPU gate (V-RAM-005 / X-DRV-003, the CUDA-moat-escape thesis in miniature on the sovereign GPU-class device). Proves: (1) GPU-COMPUTE -- the CANONICAL op-list emitter nx_drv_proto_emit, driven by gpu_compute_virt.spec alone (zero emitter change), authors a SPIR-V-gated DOT8 compute driver; the sovereign rv64 emu (+ rv64im_min_gpu) runs it: enable -> bind ring -> lay a DOT8 packet (SPIR-V magic + two int8 vectors a=[3,2,5,1] b=[4,6,1,2]) -> doorbell -> the device validates the SPIR-V magic, computes dot=sum(a[i]*b[i]) and latches RESULTPEEK -> the driver reads it back == 0x1f. Serial CONTAINS golden "GPUENRINGCMDDOT" + a clean halt. (2) BIT-IDENTICAL -- the gate computes the SAME int8 dot product on the CPU (independent loop) and asserts it == the value the GPU round-trip verified (0x1f=31). CPU lane == GPU lane, MEASURED. (3) INPUT-TAMPER -- bump a[0] (3->4) in the spec, re-emit, re-run: the device computes a DIFFERENT dot (35) so the driver's RESULTPEEK read-back verify fails -> the golden drops. This proves the device REALLY computes from the input data (not a stuck constant) -- the no-false-green handle. (4) DISTINCT -- the SAME emitter binary, driven by the echo GPU op-list, yields a different golden. Every verdict is a PRINTED marker off a REAL sovereign run; raw bytes read SOVEREIGNLY (sys_read). NO qemu/gcc/openssl/python. Marker -> knowledge/status/driver_spec.log (GPUCOMPUTEGATE row). Sovereign orchestration (fork/dup3/execve/wait4). license_tier: ORIGINAL

dependencies 1 imports · 0 importers

nx_syscalls.nx _gpu_compute_gate.nx

imports: nx_syscalls.nx

imported by: nobody (leaf or entry point)

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

main q_p sys_write sys_openat_append sys_mmap q_emit_run q_run1 sys_fork sys_openat_wr sys_dup3 sys_mmap ↻ sys_execve sys_exit sys_wait4 q_read sys_openat_rd sys_read sys_close sys_mmap ↻ q_buf_has q_run1 ↻ q_read ↻ q_strlen q_streq sys_openat_wr ↻ sys_write ↻ sys_close ↻ q_buf_has ↻ q_fn sys_mmap ↻ sys_write ↻ q_fp sys_write ↻ sys_now_realtime_sec sys_mmap ↻ sys_clock_gettime_real sys_exit ↻

structs

none

consts

21const EMIT_ELF: *u8 = "_offc/nx_drv_proto_emit.elf"
22const SOV_ELF: *u8 = "_offc/_gpu_run.elf"

functions

24func q_p(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 }
called by 1: main calls 1: sys_write
25func q_fp(fd: i64, s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(fd,s,n); return 0 }
called by 1: main calls 1: sys_write
26func q_fn(fd: i64, v: i64) -> i64 { let bb: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m}; let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48;k=1}; while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1}; var i: i64=0; while i<k{bb[i]=t[k-1-i];i=i+1}; sys_write(fd,bb,k); return 0 }
called by 1: main calls 2: sys_mmapsys_write
28func q_run1(prog: *u8, a1: *u8, outpath: *u8) -> i64
49func q_read(path: *u8, buf: *u8, cap: i64) -> i64
59func q_buf_has(buf: *u8, n: i64, pat: *u8, pl: i64) -> i64
called by 2: q_emit_runmain
71func q_strlen(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} return n }
called by 1: main
73func q_streq(a: *u8, b: *u8) -> i64
called by 1: main
81func q_emit_run(spec: *u8, out: *u8, goldout: *u8, gbuf: *u8, gcap: i64, serialpath: *u8) -> i64
called by 1: main calls 4: q_run1q_readsys_mmapq_buf_has
96func main() -> i64