code wiki / _hdl_build / _gpu_dxg_syncobj_gate.nx

_gpu_dxg_syncobj_gate.nx

buildroot/runtime/_hdl_build/_gpu_dxg_syncobj_gate.nx

12123 B146 linesdepth 2pulls 2 transitivereach 0 importersview sourcekind gate/prooftopic gpu
docsdependenciesstructsconstsfunctions

about

_gpu_dxg_syncobj_gate.nx -- SOVEREIGN-GPU ladder R4g (GPU synchronization-object mechanism on the 5080). SUBMITCOMMAND (0x0f) forwards the command buffer UNINSPECTED to the host -> a real submit needs NVIDIA GPU-ISA command packets (an empty submit would fault/TDR the GPU) = the R5 frontier. The SAFE, real mechanism rung is the GPU sync fabric: create a MONITORED FENCE and round-trip it CPU-side (create -> signal -> wait completes). ABI (size-swept LIVE): CREATESYNCHRONIZATIONOBJECT = 0xC0604710 (size 96; device@0, info.type@8=5 MONITORED_FENCE, union@16: initial@16 / fence_cpu_va@24 OUT / fence_gpu_va@32 OUT; sync_object@88 OUT). SIGNALSYNCHRONIZATIONOBJECTFROMCPU = 0xC0204731 (size 32; device@0, object_count@4, objects@8 ptr, fence_values@16 ptr). WAITFORSYNCHRONIZATIONOBJECTFROMCPU = 0xC028473A (size 40; +async_event@24=0 => synchronous). FINDINGS (honest): the fence_cpu_va page mirrors GPU-engine signals, NOT CPU-side signals (stays 0 here); and SIGNAL-from-CPU is fire-and-forget (doesn't validate the handle locally). So the proof uses what IS verifiable: type-validated create + signal->wait round-trip completion + WAIT/count/fd validation. GREEN iff (author=organ, from REAL device returns): A) chain ok; create MONITORED_FENCE ret==0 AND sync_object != 0 AND fence_cpu_va != 0 (real kernel-mapped page); B) create with an INVALID type (99) is REJECTED (negative) -> the create is type-sensitive, not a blind success; C) signal(so,5)==0 AND signal(so,9)==0 AND sync-wait(so,9)==0 -- the create->signal->wait round-trip COMPLETES (a sync wait for an unreached value would block; it returns, so the signals advanced the real fence to 9); D) TAMPER (validated negatives, so wait isn't a blind return-0): wait(bogus handle) -> neg; signal(object_count=0) -> neg; wait on a non-dxg fd -> -ENOTTY. Marker -> knowledge/status/gpu_dxg.log (DXGSYNCGATE). raw syscalls only. NO-WAVE: sync-object mechanism only; the command-buffer SUBMIT path is NVIDIA GPU-ISA (R5), explicitly out of scope. ZERO compute/throughput. license_tier: ORIGINAL

dependencies 1 imports · 0 importers

nx_syscalls.nx _gpu_dxg_syncobj_gate.nx

imports: nx_syscalls.nx

imported by: nobody (leaf or entry point)

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

main p sys_write sys_openat_rd sys_exit sys_mmap sys_ioctl rd32 query_type sys_mmap ↻ sys_ioctl ↻ rd32 ↻ open_from_luid sys_mmap ↻ sys_ioctl ↻ rd32 ↻ create_device sys_mmap ↻ setu32 sys_ioctl ↻ rd32 ↻ create_so sys_mmap ↻ setu32 ↻ sys_ioctl ↻ rd32 ↻ rd64 x p ↻ sys_mmap ↻ sys_write ↻ n sys_mmap ↻ sys_write ↻ signal_cpu sys_mmap ↻ setu32 ↻ setu64 sys_ioctl ↻ wait_cpu

structs

none

consts

27const ENUM2_CODE: i64 = 0xC0104714
28const QAI_CODE: i64 = 0xC0184709
29const OAFL_CODE: i64 = 0xC00C4701
30const CDEV_CODE: i64 = 0xC0404702
31const CSO_CODE: i64 = 0xC0604710
32const SIG_CODE: i64 = 0xC0204731
33const WAIT_CODE: i64 = 0xC028473A

functions

35func p(s: *u8) -> i64 { var nn: i64=0; while s[nn]!=(0 as u8){nn=nn+1} sys_write(1,s,nn); return 0 }
called by 2: xmain calls 1: sys_write
36func fp(fd: i64, s: *u8) -> i64 { var nn: i64=0; while s[nn]!=(0 as u8){nn=nn+1} sys_write(fd,s,nn); return 0 }
called by 2: fxmain calls 1: sys_write
37func n(v: i64) -> i64 { let bb: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m;sys_write(1,"-" as *u8,1)}; let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48;k=1}; while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1}; var i: i64=0; while i<k{bb[i]=t[k-1-i];i=i+1}; sys_write(1,bb,k); return 0 }
called by 1: main calls 2: sys_mmapsys_write
38func x(v: i64) -> i64 { p("0x" as *u8); let bb:*u8=sys_mmap(20); var k:i64=0; var m:i64=v; if m==0{bb[0]=48;k=1}; while m>0{ let d:i64=m&15; if d<10{bb[k]=(48+d) as u8}else{bb[k]=(87+d) as u8}; m=(m>>4); k=k+1 } var i:i64=0; let o:*u8=sys_mmap(20); while i<k{o[i]=bb[k-1-i];i=i+1} sys_write(1,o,k); return 0 }
called by 1: main calls 3: psys_mmapsys_write
39func fx(fd: i64, v: i64) -> i64 { let bb:*u8=sys_mmap(20); var k:i64=0; var m:i64=v; if m==0{bb[0]=48;k=1}; while m>0{ let d:i64=m&15; if d<10{bb[k]=(48+d) as u8}else{bb[k]=(87+d) as u8}; m=(m>>4); k=k+1 } let o:*u8=sys_mmap(20); var i:i64=0; while i<k{o[i]=bb[k-1-i];i=i+1} fp(fd,"0x" as *u8); sys_write(fd,o,k); return 0 }
called by 1: main calls 3: sys_mmapfpsys_write
40func rd32(buf: *u8, off: i64) -> i64 { return (buf[off] as i64)|((buf[off+1] as i64)<<8)|((buf[off+2] as i64)<<16)|((buf[off+3] as i64)<<24) }
41func rd64(buf: *u8, off: i64) -> i64 { let q: *i64 = (buf as i64 + off) as *i64; return q[0] }
called by 1: create_so
42func setu32(buf: *u8, off: i64, val: i64) -> i64 { let w: *u8 = (buf as i64 + off) as *u8; w[0]=(val&0xff) as u8; w[1]=((val>>8)&0xff) as u8; w[2]=((val>>16)&0xff) as u8; w[3]=((val>>24)&0xff) as u8; return 0 }
43func setu64(buf: *u8, off: i64, val: i64) -> i64 { let q: *i64 = (buf as i64 + off) as *i64; q[0]=val; return 0 }
called by 2: signal_cpuwait_cpu
45func query_type(fd: i64, handle: i64, qtype: i64, psize: i64, outv: *i64) -> i64
called by 1: main calls 3: sys_mmapsys_ioctlrd32
53func open_from_luid(fd: i64, luid_lo: i64, luid_hi: i64, outh: *i64) -> i64
called by 1: main calls 3: sys_mmapsys_ioctlrd32
58func create_device(fd: i64, adapter: i64, outd: *i64) -> i64
called by 1: main calls 4: sys_mmapsetu32sys_ioctlrd32
64func create_so(fd: i64, device: i64, stype: i64, outso: *i64, outfva: *i64) -> i64
69func signal_cpu(fd: i64, code: i64, device: i64, so: i64, count: i64, val: i64) -> i64
called by 1: main calls 4: sys_mmapsetu32setu64sys_ioctl
76func wait_cpu(fd: i64, device: i64, so: i64, val: i64) -> i64
called by 1: main calls 4: sys_mmapsetu32setu64sys_ioctl
84func main() -> i64