_gpu_dxg_syncobj_gate.nx source

1// _gpu_dxg_syncobj_gate.nx -- SOVEREIGN-GPU ladder R4g (GPU synchronization-object mechanism on the 5080). 2// 3// SUBMITCOMMAND (0x0f) forwards the command buffer UNINSPECTED to the host -> a real submit needs NVIDIA GPU-ISA 4// command packets (an empty submit would fault/TDR the GPU) = the R5 frontier. The SAFE, real mechanism rung is 5// the GPU sync fabric: create a MONITORED FENCE and round-trip it CPU-side (create -> signal -> wait completes). 6// 7// ABI (size-swept LIVE): CREATESYNCHRONIZATIONOBJECT = 0xC0604710 (size 96; device@0, info.type@8=5 MONITORED_FENCE, 8// union@16: initial@16 / fence_cpu_va@24 OUT / fence_gpu_va@32 OUT; sync_object@88 OUT). 9// SIGNALSYNCHRONIZATIONOBJECTFROMCPU = 0xC0204731 (size 32; device@0, object_count@4, objects@8 ptr, fence_values@16 ptr). 10// WAITFORSYNCHRONIZATIONOBJECTFROMCPU = 0xC028473A (size 40; +async_event@24=0 => synchronous). 11// FINDINGS (honest): the fence_cpu_va page mirrors GPU-engine signals, NOT CPU-side signals (stays 0 here); and 12// SIGNAL-from-CPU is fire-and-forget (doesn't validate the handle locally). So the proof uses what IS verifiable: 13// type-validated create + signal->wait round-trip completion + WAIT/count/fd validation. 14// 15// GREEN iff (author=organ, from REAL device returns): 16// A) chain ok; create MONITORED_FENCE ret==0 AND sync_object != 0 AND fence_cpu_va != 0 (real kernel-mapped page); 17// B) create with an INVALID type (99) is REJECTED (negative) -> the create is type-sensitive, not a blind success; 18// C) signal(so,5)==0 AND signal(so,9)==0 AND sync-wait(so,9)==0 -- the create->signal->wait round-trip COMPLETES 19// (a sync wait for an unreached value would block; it returns, so the signals advanced the real fence to 9); 20// D) TAMPER (validated negatives, so wait isn't a blind return-0): wait(bogus handle) -> neg; signal(object_count=0) -> neg; 21// wait on a non-dxg fd -> -ENOTTY. 22// Marker -> knowledge/status/gpu_dxg.log (DXGSYNCGATE). raw syscalls only. NO-WAVE: sync-object mechanism only; the 23// command-buffer SUBMIT path is NVIDIA GPU-ISA (R5), explicitly out of scope. ZERO compute/throughput. 24// license_tier: ORIGINAL 25import "nx_syscalls.nx" 26 27const ENUM2_CODE: i64 = 0xC0104714 28const QAI_CODE: i64 = 0xC0184709 29const OAFL_CODE: i64 = 0xC00C4701 30const CDEV_CODE: i64 = 0xC0404702 31const CSO_CODE: i64 = 0xC0604710 32const SIG_CODE: i64 = 0xC0204731 33const WAIT_CODE: i64 = 0xC028473A 34 35func p(s: *u8) -> i64 { var nn: i64=0; while s[nn]!=(0 as u8){nn=nn+1} sys_write(1,s,nn); return 0 } 36func fp(fd: i64, s: *u8) -> i64 { var nn: i64=0; while s[nn]!=(0 as u8){nn=nn+1} sys_write(fd,s,nn); return 0 } 37func n(v: i64) -> i64 { let bb: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m;sys_write(1,"-" as *u8,1)}; let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48;k=1}; while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1}; var i: i64=0; while i<k{bb[i]=t[k-1-i];i=i+1}; sys_write(1,bb,k); return 0 } 38func x(v: i64) -> i64 { p("0x" as *u8); let bb:*u8=sys_mmap(20); var k:i64=0; var m:i64=v; if m==0{bb[0]=48;k=1}; while m>0{ let d:i64=m&15; if d<10{bb[k]=(48+d) as u8}else{bb[k]=(87+d) as u8}; m=(m>>4); k=k+1 } var i:i64=0; let o:*u8=sys_mmap(20); while i<k{o[i]=bb[k-1-i];i=i+1} sys_write(1,o,k); return 0 } 39func fx(fd: i64, v: i64) -> i64 { let bb:*u8=sys_mmap(20); var k:i64=0; var m:i64=v; if m==0{bb[0]=48;k=1}; while m>0{ let d:i64=m&15; if d<10{bb[k]=(48+d) as u8}else{bb[k]=(87+d) as u8}; m=(m>>4); k=k+1 } let o:*u8=sys_mmap(20); var i:i64=0; while i<k{o[i]=bb[k-1-i];i=i+1} fp(fd,"0x" as *u8); sys_write(fd,o,k); return 0 } 40func rd32(buf: *u8, off: i64) -> i64 { return (buf[off] as i64)|((buf[off+1] as i64)<<8)|((buf[off+2] as i64)<<16)|((buf[off+3] as i64)<<24) } 41func rd64(buf: *u8, off: i64) -> i64 { let q: *i64 = (buf as i64 + off) as *i64; return q[0] } 42func setu32(buf: *u8, off: i64, val: i64) -> i64 { let w: *u8 = (buf as i64 + off) as *u8; w[0]=(val&0xff) as u8; w[1]=((val>>8)&0xff) as u8; w[2]=((val>>16)&0xff) as u8; w[3]=((val>>24)&0xff) as u8; return 0 } 43func setu64(buf: *u8, off: i64, val: i64) -> i64 { let q: *i64 = (buf as i64 + off) as *i64; q[0]=val; return 0 } 44 45func query_type(fd: i64, handle: i64, qtype: i64, psize: i64, outv: *i64) -> i64 { 46 let priv: *u8 = sys_mmap(64); var zz: i64 = 0; while zz < 64 { priv[zz] = 0 as u8; zz = zz + 1 } 47 let req: *u8 = sys_mmap(64); var y: i64 = 0; while y < 64 { req[y] = 0 as u8; y = y + 1 } 48 let h: *i64 = (req as i64 + 0) as *i64; h[0] = (handle & 0xffffffff) | ((qtype & 0xffffffff) << 32) 49 let pd: *i64 = (req as i64 + 8) as *i64; pd[0] = priv as i64 50 let pds: *i64 = (req as i64 + 16) as *i64; pds[0] = psize & 0xffffffff 51 let ret: i64 = sys_ioctl(fd, QAI_CODE, req as i64); outv[0] = rd32(priv, 0); return ret 52} 53func open_from_luid(fd: i64, luid_lo: i64, luid_hi: i64, outh: *i64) -> i64 { 54 let req: *u8 = sys_mmap(64); var y: i64 = 0; while y < 64 { req[y] = 0 as u8; y = y + 1 } 55 let lo: *i64 = (req as i64 + 0) as *i64; lo[0] = (luid_lo & 0xffffffff) | ((luid_hi & 0xffffffff) << 32) 56 let ret: i64 = sys_ioctl(fd, OAFL_CODE, req as i64); outh[0] = rd32(req, 8); return ret 57} 58func create_device(fd: i64, adapter: i64, outd: *i64) -> i64 { 59 let buf: *u8 = sys_mmap(512); var bz: i64 = 0; while bz < 512 { buf[bz] = 0 as u8; bz = bz + 1 } 60 setu32(buf, 0, adapter & 0xffffffff) 61 let ret: i64 = sys_ioctl(fd, CDEV_CODE, buf as i64); outd[0] = rd32(buf, 12); return ret 62} 63// create a sync object of `stype`. OUT sync_object@88 -> outso[0], fence_cpu_va@24 -> outfva[0]. 64func create_so(fd: i64, device: i64, stype: i64, outso: *i64, outfva: *i64) -> i64 { 65 let buf: *u8 = sys_mmap(512); var bz: i64 = 0; while bz < 512 { buf[bz] = 0 as u8; bz = bz + 1 } 66 setu32(buf, 0, device & 0xffffffff); setu32(buf, 8, stype) 67 let ret: i64 = sys_ioctl(fd, CSO_CODE, buf as i64); outso[0] = rd32(buf, 88); outfva[0] = rd64(buf, 24); return ret 68} 69func signal_cpu(fd: i64, code: i64, device: i64, so: i64, count: i64, val: i64) -> i64 { 70 let objs: *u8 = sys_mmap(64); setu32(objs, 0, so & 0xffffffff) 71 let vals: *u8 = sys_mmap(64); setu64(vals, 0, val) 72 let buf: *u8 = sys_mmap(128); var bz: i64 = 0; while bz < 128 { buf[bz] = 0 as u8; bz = bz + 1 } 73 setu32(buf, 0, device & 0xffffffff); setu32(buf, 4, count); setu64(buf, 8, objs as i64); setu64(buf, 16, vals as i64) 74 return sys_ioctl(fd, code, buf as i64) 75} 76func wait_cpu(fd: i64, device: i64, so: i64, val: i64) -> i64 { 77 let objs: *u8 = sys_mmap(64); setu32(objs, 0, so & 0xffffffff) 78 let vals: *u8 = sys_mmap(64); setu64(vals, 0, val) 79 let buf: *u8 = sys_mmap(128); var bz: i64 = 0; while bz < 128 { buf[bz] = 0 as u8; bz = bz + 1 } 80 setu32(buf, 0, device & 0xffffffff); setu32(buf, 4, 1); setu64(buf, 8, objs as i64); setu64(buf, 16, vals as i64) 81 return sys_ioctl(fd, WAIT_CODE, buf as i64) // async_event@24=0 -> sync; only ever waits for an already-reached value 82} 83 84func main() -> i64 { 85 p("=== SOVEREIGN-GPU R4g gate (raw /dev/dxg monitored-fence sync object: create + CPU signal + CPU wait on the 5080) ===\n" as *u8) 86 let fd: i64 = sys_openat_rd("/dev/dxg" as *u8) 87 if fd < 0 { p("open(/dev/dxg) failed\n" as *u8); sys_exit(1); return 1 } 88 let ainfo: *u8 = sys_mmap(4096); var z: i64 = 0; while z < 4096 { ainfo[z] = 0 as u8; z = z + 1 } 89 let ereq: *u8 = sys_mmap(64); ereq[0] = 8 as u8; let r8: *i64 = (ereq as i64 + 8) as *i64; r8[0] = ainfo as i64 90 let eret: i64 = sys_ioctl(fd, ENUM2_CODE, ereq as i64); let nc: i64 = rd32(ereq, 0) 91 let v: *i64 = sys_mmap(16); var n_discrete: i64 = 0; var disc_lo: i64 = 0; var disc_hi: i64 = 0 92 var ai: i64 = 0 93 while ai < nc { 94 let base: i64 = ai * 20; let eh: i64 = rd32(ainfo, base) 95 let qret: i64 = query_type(fd, eh, 15, 4, v); let t: i64 = v[0] 96 if qret == 0 { if ((t>>4)&1) == 1 { if ((t>>2)&1) == 0 { n_discrete = n_discrete + 1; disc_lo = rd32(ainfo, base+4); disc_hi = rd32(ainfo, base+8) } } } 97 ai = ai + 1 98 } 99 let ah: *i64 = sys_mmap(16); let aor: i64 = open_from_luid(fd, disc_lo, disc_hi, ah) 100 let dh: *i64 = sys_mmap(16); let dr: i64 = create_device(fd, ah[0], dh); let device: i64 = dh[0] 101 let soh: *i64 = sys_mmap(16); let fvah: *i64 = sys_mmap(16); let cr: i64 = create_so(fd, device, 5, soh, fvah); let so: i64 = soh[0]; let fence_va: i64 = fvah[0] 102 // type-validation discrimination: an invalid sync object type must be rejected. 103 let bso: *i64 = sys_mmap(16); let bfva: *i64 = sys_mmap(16); let cr_bad: i64 = create_so(fd, device, 99, bso, bfva) 104 p(" chain: device=" as *u8); x(device); p(" create(type5) ret=" as *u8); n(cr); p(" sync_object=" as *u8); x(so); p(" fence_cpu_va=" as *u8); x(fence_va); p(" | create(type99) ret=" as *u8); n(cr_bad); p("\n" as *u8) 105 106 let rs1: i64 = signal_cpu(fd, SIG_CODE, device, so, 1, 5) 107 let rs2: i64 = signal_cpu(fd, SIG_CODE, device, so, 1, 9) 108 let rw: i64 = wait_cpu(fd, device, so, 9) 109 p(" signal(5)=" as *u8); n(rs1); p(" signal(9)=" as *u8); n(rs2); p(" sync-wait(9)=" as *u8); n(rw); p(" (round-trip completed = signals advanced the real fence)\n" as *u8) 110 111 // ---- TAMPER matrix (validated negatives) ---- 112 let t1: i64 = wait_cpu(fd, device, 0xdeadbeef, 1) // wait bogus sync object (handle validated before any block) 113 let t2: i64 = signal_cpu(fd, SIG_CODE, device, so, 0, 1) // signal object_count = 0 114 let nfd: i64 = sys_openat_rd("/dev/null" as *u8) 115 let t3: i64 = wait_cpu(nfd, device, so, 9) // wait on non-dxg fd 116 if nfd >= 0 { sys_close(nfd) } 117 p(" [tamper] wait-bogus-obj=" as *u8); n(t1); p(" | signal-count0=" as *u8); n(t2); p(" | wait-non-dxg=" as *u8); n(t3); p("\n" as *u8) 118 sys_close(fd) 119 120 var created: i64 = 0; if cr == 0 { if so != 0 { if fence_va != 0 { created = 1 } } } 121 var type_validated: i64 = 0; if cr_bad < 0 { type_validated = 1 } 122 var roundtrip: i64 = 0; if rs1 == 0 { if rs2 == 0 { if rw == 0 { roundtrip = 1 } } } 123 var tamper_ok: i64 = 0; if t1 < 0 { if t2 < 0 { if t3 < 0 { tamper_ok = 1 } } } 124 125 var pass: i64 = 0 126 if eret == 0 { if n_discrete == 1 { if aor == 0 { if dr == 0 { 127 if created == 1 { if type_validated == 1 { if roundtrip == 1 { if tamper_ok == 1 { pass = 1 } } } } } } } } 128 129 p(" checks: chain_ok=" as *u8); var ch: i64=0; if eret==0 { if aor==0 { if dr==0 { ch=1 } } } n(ch) 130 p(" mf_created=" as *u8); n(created); p(" type_validated(99-rejected)=" as *u8); n(type_validated); p(" signal_wait_roundtrip=" as *u8); n(roundtrip); p(" tamper_ok=" as *u8); n(tamper_ok); p("\n" as *u8) 131 132 let lfd: i64 = sys_openat_append("knowledge/status/gpu_dxg.log" as *u8, 0x1a4) 133 if pass == 1 { 134 p("DXGSYNCGATE verdict=GREEN reason=raw-/dev/dxg-monitored-fence-sync-object-create+CPU-signal+CPU-wait-on-the-5080 (type-validated create [type99 rejected]; real sync_object+kernel-mapped fence page; signal->signal->sync-wait(9) round-trip COMPLETES = the signals advanced the real fence; wait validates [bogus-obj/count0/non-dxg all negative]; wrapper-free) SCOPE=gpu-sync-object-mechanism-only-NO-throughput; command-buffer-SUBMIT=NVIDIA-GPU-ISA=R5\n" as *u8) 135 if lfd >= 0 { 136 fp(lfd, "DXGSYNCGATE verdict=GREEN rung=R4g-gpu-sync-object device=discrete-RTX5080 via=raw-/dev/dxg-CREATESYNCHRONIZATIONOBJECT(0xC0604710,size96,monitored-fence,sync@88)+SIGNALFROMCPU(0xC0204731,size32)+WAITFROMCPU(0xC028473A,size40) sync_object=" as *u8); fx(lfd, so) 137 fp(lfd, " fence_cpu_va=" as *u8); fx(lfd, fence_va); fp(lfd, " type99_rejected=1 signal+sync-wait(9)_roundtrip=ok tamper=rejected(wait-bogus-obj+signal-count0+wait-non-dxg) wrapper-free scope=sync-object-mechanism-only-NO-throughput NOTE=SUBMITCOMMAND-forwards-buffer-UNINSPECTED-to-host=NVIDIA-GPU-ISA=R5-frontier; fence_cpu_va-mirrors-GPU-not-CPU-signals\n" as *u8) 138 sys_close(lfd) 139 } 140 sys_exit(0); return 0 141 } 142 p("DXGSYNCGATE verdict=RED (one of chain/create/type-validate/roundtrip/tamper not satisfied)\n" as *u8) 143 if lfd >= 0 { fp(lfd, "DXGSYNCGATE verdict=RED see-console\n" as *u8); sys_close(lfd) } 144 sys_exit(1) 145 return 1 146}