code wiki / _hdl_build / _gpu_dxg_r4e_wait_recon.nx

_gpu_dxg_r4e_wait_recon.nx

buildroot/runtime/_hdl_build/_gpu_dxg_r4e_wait_recon.nx

7289 B101 linesdepth 2pulls 2 transitivereach 0 importersview sourcekind tooltopic gpu
docsdependenciesstructsconstsfunctions

about

_gpu_dxg_r4e_wait_recon.nx -- SOVEREIGN-GPU R4e RECON: confirm the paging fence ADVANCES to the map's paging_fence_value (i.e. the GPU actually completes the async VA mapping). Chain: device -> paging queue (capture fence_cpu_virtual_address@16) -> EXISTINGHEAP alloc -> MAPGPUVIRTUALADDRESS (ret=259 STATUS_PENDING, returns gpu_va + paging_fence_value) -> spin-read *(u64*)fence_cpu_va until it reaches paging_fence_value. Print initial fence, target, final fence, iters. raw syscalls only. license_tier: ORIGINAL

dependencies 1 imports · 0 importers

nx_syscalls.nx _gpu_dxg_r4e_wait_recon.nx

imports: nx_syscalls.nx

imported by: nobody (leaf or entry point)

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

main p sys_write sys_openat_rd sys_exit sys_mmap sys_ioctl rd32 query_type sys_mmap ↻ sys_ioctl ↻ rd32 ↻ open_from_luid sys_mmap ↻ sys_ioctl ↻ rd32 ↻ create_device sys_mmap ↻ setu32 sys_ioctl ↻ rd32 ↻ create_pq sys_mmap ↻ setu32 ↻ sys_ioctl ↻ rd32 ↻ rd64 alloc_eh sys_mmap ↻ setu32 ↻ setu64 sys_ioctl ↻ rd32 ↻ map_va sys_mmap ↻ setu32 ↻ setu64 ↻ sys_ioctl ↻ rd64 ↻ n

structs

none

consts

8const ENUM2_CODE: i64 = 0xC0104714
9const QAI_CODE: i64 = 0xC0184709
10const OAFL_CODE: i64 = 0xC00C4701
11const CDEV_CODE: i64 = 0xC0404702
12const CPQ_CODE: i64 = 0xC0204707
13const CALLOC_CODE: i64 = 0xC0484706
14const MAPVA_CODE: i64 = 0xC068470C

functions

16func p(s: *u8) -> i64 { var nn: i64=0; while s[nn]!=(0 as u8){nn=nn+1} sys_write(1,s,nn); return 0 }
called by 2: xmain calls 1: sys_write
17func n(v: i64) -> i64 { let bb: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m;sys_write(1,"-" as *u8,1)}; let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48;k=1}; while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1}; var i: i64=0; while i<k{bb[i]=t[k-1-i];i=i+1}; sys_write(1,bb,k); return 0 }
called by 1: main calls 2: sys_mmapsys_write
18func x(v: i64) -> i64 { p("0x" as *u8); let bb:*u8=sys_mmap(20); var k:i64=0; var m:i64=v; if m==0{bb[0]=48;k=1}; while m>0{ let d:i64=m&15; if d<10{bb[k]=(48+d) as u8}else{bb[k]=(87+d) as u8}; m=(m>>4); k=k+1 } var i:i64=0; let o:*u8=sys_mmap(20); while i<k{o[i]=bb[k-1-i];i=i+1} sys_write(1,o,k); return 0 }
called by 1: main calls 3: psys_mmapsys_write
19func rd32(buf: *u8, off: i64) -> i64 { return (buf[off] as i64)|((buf[off+1] as i64)<<8)|((buf[off+2] as i64)<<16)|((buf[off+3] as i64)<<24) }
20func rd64(buf: *u8, off: i64) -> i64 { let q: *i64 = (buf as i64 + off) as *i64; return q[0] }
called by 2: create_pqmap_va
21func setu32(buf: *u8, off: i64, val: i64) -> i64 { let w: *u8 = (buf as i64 + off) as *u8; w[0]=(val&0xff) as u8; w[1]=((val>>8)&0xff) as u8; w[2]=((val>>16)&0xff) as u8; w[3]=((val>>24)&0xff) as u8; return 0 }
22func setu64(buf: *u8, off: i64, val: i64) -> i64 { let q: *i64 = (buf as i64 + off) as *i64; q[0]=val; return 0 }
called by 2: alloc_ehmap_va
24func query_type(fd: i64, handle: i64, qtype: i64, psize: i64, outv: *i64) -> i64
called by 1: main calls 3: sys_mmapsys_ioctlrd32
32func open_from_luid(fd: i64, luid_lo: i64, luid_hi: i64, outh: *i64) -> i64
called by 1: main calls 3: sys_mmapsys_ioctlrd32
37func create_device(fd: i64, adapter: i64, outd: *i64) -> i64
called by 1: main calls 4: sys_mmapsetu32sys_ioctlrd32
43func create_pq(fd: i64, device: i64, outpq: *i64, outfva: *i64) -> i64
48func alloc_eh(fd: i64, device: i64, sysmem: *u8, outh: *i64) -> i64
58func map_va(fd: i64, pq: i64, alloc: i64, outva: *i64, outf: *i64) -> i64
66func main() -> i64