_gpu_dxg_r4e_wait_recon.nx source

1// _gpu_dxg_r4e_wait_recon.nx -- SOVEREIGN-GPU R4e RECON: confirm the paging fence ADVANCES to the map's 2// paging_fence_value (i.e. the GPU actually completes the async VA mapping). Chain: device -> paging queue 3// (capture fence_cpu_virtual_address@16) -> EXISTINGHEAP alloc -> MAPGPUVIRTUALADDRESS (ret=259 STATUS_PENDING, 4// returns gpu_va + paging_fence_value) -> spin-read *(u64*)fence_cpu_va until it reaches paging_fence_value. 5// Print initial fence, target, final fence, iters. raw syscalls only. license_tier: ORIGINAL 6import "nx_syscalls.nx" 7 8const ENUM2_CODE: i64 = 0xC0104714 9const QAI_CODE: i64 = 0xC0184709 10const OAFL_CODE: i64 = 0xC00C4701 11const CDEV_CODE: i64 = 0xC0404702 12const CPQ_CODE: i64 = 0xC0204707 13const CALLOC_CODE: i64 = 0xC0484706 14const MAPVA_CODE: i64 = 0xC068470C 15 16func p(s: *u8) -> i64 { var nn: i64=0; while s[nn]!=(0 as u8){nn=nn+1} sys_write(1,s,nn); return 0 } 17func n(v: i64) -> i64 { let bb: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m;sys_write(1,"-" as *u8,1)}; let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48;k=1}; while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1}; var i: i64=0; while i<k{bb[i]=t[k-1-i];i=i+1}; sys_write(1,bb,k); return 0 } 18func x(v: i64) -> i64 { p("0x" as *u8); let bb:*u8=sys_mmap(20); var k:i64=0; var m:i64=v; if m==0{bb[0]=48;k=1}; while m>0{ let d:i64=m&15; if d<10{bb[k]=(48+d) as u8}else{bb[k]=(87+d) as u8}; m=(m>>4); k=k+1 } var i:i64=0; let o:*u8=sys_mmap(20); while i<k{o[i]=bb[k-1-i];i=i+1} sys_write(1,o,k); return 0 } 19func rd32(buf: *u8, off: i64) -> i64 { return (buf[off] as i64)|((buf[off+1] as i64)<<8)|((buf[off+2] as i64)<<16)|((buf[off+3] as i64)<<24) } 20func rd64(buf: *u8, off: i64) -> i64 { let q: *i64 = (buf as i64 + off) as *i64; return q[0] } 21func setu32(buf: *u8, off: i64, val: i64) -> i64 { let w: *u8 = (buf as i64 + off) as *u8; w[0]=(val&0xff) as u8; w[1]=((val>>8)&0xff) as u8; w[2]=((val>>16)&0xff) as u8; w[3]=((val>>24)&0xff) as u8; return 0 } 22func setu64(buf: *u8, off: i64, val: i64) -> i64 { let q: *i64 = (buf as i64 + off) as *i64; q[0]=val; return 0 } 23 24func query_type(fd: i64, handle: i64, qtype: i64, psize: i64, outv: *i64) -> i64 { 25 let priv: *u8 = sys_mmap(64); var zz: i64 = 0; while zz < 64 { priv[zz] = 0 as u8; zz = zz + 1 } 26 let req: *u8 = sys_mmap(64); var y: i64 = 0; while y < 64 { req[y] = 0 as u8; y = y + 1 } 27 let h: *i64 = (req as i64 + 0) as *i64; h[0] = (handle & 0xffffffff) | ((qtype & 0xffffffff) << 32) 28 let pd: *i64 = (req as i64 + 8) as *i64; pd[0] = priv as i64 29 let pds: *i64 = (req as i64 + 16) as *i64; pds[0] = psize & 0xffffffff 30 let ret: i64 = sys_ioctl(fd, QAI_CODE, req as i64); outv[0] = rd32(priv, 0); return ret 31} 32func open_from_luid(fd: i64, luid_lo: i64, luid_hi: i64, outh: *i64) -> i64 { 33 let req: *u8 = sys_mmap(64); var y: i64 = 0; while y < 64 { req[y] = 0 as u8; y = y + 1 } 34 let lo: *i64 = (req as i64 + 0) as *i64; lo[0] = (luid_lo & 0xffffffff) | ((luid_hi & 0xffffffff) << 32) 35 let ret: i64 = sys_ioctl(fd, OAFL_CODE, req as i64); outh[0] = rd32(req, 8); return ret 36} 37func create_device(fd: i64, adapter: i64, outd: *i64) -> i64 { 38 let buf: *u8 = sys_mmap(512); var bz: i64 = 0; while bz < 512 { buf[bz] = 0 as u8; bz = bz + 1 } 39 setu32(buf, 0, adapter & 0xffffffff) 40 let ret: i64 = sys_ioctl(fd, CDEV_CODE, buf as i64); outd[0] = rd32(buf, 12); return ret 41} 42// create paging queue; OUT pq@8 -> outpq[0], fence_cpu_va@16 -> outfva[0] 43func create_pq(fd: i64, device: i64, outpq: *i64, outfva: *i64) -> i64 { 44 let buf: *u8 = sys_mmap(512); var bz: i64 = 0; while bz < 512 { buf[bz] = 0 as u8; bz = bz + 1 } 45 setu32(buf, 0, device & 0xffffffff) 46 let ret: i64 = sys_ioctl(fd, CPQ_CODE, buf as i64); outpq[0] = rd32(buf, 8); outfva[0] = rd64(buf, 16); return ret 47} 48func alloc_eh(fd: i64, device: i64, sysmem: *u8, outh: *i64) -> i64 { 49 let desc: *u8 = sys_mmap(64); var dz: i64 = 0; while dz < 64 { desc[dz] = 0 as u8; dz = dz + 1 } 50 setu32(desc, 0, 1); setu64(desc, 8, 65536) 51 let entry: *u8 = sys_mmap(256); var ez: i64 = 0; while ez < 256 { entry[ez] = 0 as u8; ez = ez + 1 } 52 setu64(entry, 8, sysmem as i64) 53 let buf: *u8 = sys_mmap(512); var bz: i64 = 0; while bz < 512 { buf[bz] = 0 as u8; bz = bz + 1 } 54 setu32(buf, 0, device & 0xffffffff); setu64(buf, 32, desc as i64); setu32(buf, 40, 0) 55 setu32(buf, 44, 1); setu64(buf, 48, entry as i64); setu32(buf, 56, 0x10020) 56 let ret: i64 = sys_ioctl(fd, CALLOC_CODE, buf as i64); outh[0] = rd32(entry, 0); return ret 57} 58func map_va(fd: i64, pq: i64, alloc: i64, outva: *i64, outf: *i64) -> i64 { 59 let buf: *u8 = sys_mmap(256); var bz: i64 = 0; while bz < 256 { buf[bz] = 0 as u8; bz = bz + 1 } 60 setu32(buf, 0, pq & 0xffffffff); setu64(buf, 24, 0x10000000000) 61 setu32(buf, 32, alloc & 0xffffffff); setu64(buf, 48, 16); setu64(buf, 56, 1) 62 let ret: i64 = sys_ioctl(fd, MAPVA_CODE, buf as i64) 63 outva[0] = rd64(buf, 88); outf[0] = rd64(buf, 96); return ret 64} 65 66func main() -> i64 { 67 p("=== R4e WAIT RECON: does the paging fence advance to paging_fence_value? ===\n" as *u8) 68 let fd: i64 = sys_openat_rd("/dev/dxg" as *u8) 69 if fd < 0 { p("open fail\n" as *u8); sys_exit(1); return 1 } 70 let ainfo: *u8 = sys_mmap(4096); var z: i64 = 0; while z < 4096 { ainfo[z] = 0 as u8; z = z + 1 } 71 let ereq: *u8 = sys_mmap(64); ereq[0] = 8 as u8; let r8: *i64 = (ereq as i64 + 8) as *i64; r8[0] = ainfo as i64 72 sys_ioctl(fd, ENUM2_CODE, ereq as i64); let nc: i64 = rd32(ereq, 0) 73 let v: *i64 = sys_mmap(16); var disc_lo: i64 = 0; var disc_hi: i64 = 0 74 var ai: i64 = 0 75 while ai < nc { 76 let base: i64 = ai * 20; let eh: i64 = rd32(ainfo, base) 77 let qret: i64 = query_type(fd, eh, 15, 4, v); let t: i64 = v[0] 78 if qret == 0 { if ((t>>4)&1) == 1 { if ((t>>2)&1) == 0 { disc_lo = rd32(ainfo, base+4); disc_hi = rd32(ainfo, base+8) } } } 79 ai = ai + 1 80 } 81 let ah: *i64 = sys_mmap(16); open_from_luid(fd, disc_lo, disc_hi, ah) 82 let dh: *i64 = sys_mmap(16); create_device(fd, ah[0], dh); let device: i64 = dh[0] 83 let pqh: *i64 = sys_mmap(16); let fvah: *i64 = sys_mmap(16); create_pq(fd, device, pqh, fvah); let pq: i64 = pqh[0]; let fence_va: i64 = fvah[0] 84 let sysmem: *u8 = sys_mmap(65536); var sz: i64 = 0; while sz < 65536 { sysmem[sz] = 0 as u8; sz = sz + 1 } 85 let alh: *i64 = sys_mmap(16); alloc_eh(fd, device, sysmem, alh); let alloc: i64 = alh[0] 86 87 let fp0: *i64 = fence_va as *i64; let fence_before: i64 = fp0[0] 88 let ova: *i64 = sys_mmap(16); let ofv: *i64 = sys_mmap(16) 89 let r: i64 = map_va(fd, pq, alloc, ova, ofv) 90 p(" map ret=" as *u8); n(r); p(" gpu_va=" as *u8); x(ova[0]); p(" target_fence=" as *u8); n(ofv[0]); p(" fence_before_map=" as *u8); n(fence_before); p("\n" as *u8) 91 92 // spin-read the fence page until it reaches target (bounded). 93 let target: i64 = ofv[0] 94 let fpp: *i64 = fence_va as *i64 95 var iters: i64 = 0; var cur: i64 = fpp[0]; var reached: i64 = 0 96 while iters < 500000000 { cur = fpp[0]; if cur >= target { reached = 1; iters = 500000000 } else { iters = iters + 1 } } 97 p(" after spin: fence_now=" as *u8); n(fpp[0]); p(" target=" as *u8); n(target); p(" reached=" as *u8); n(reached); p("\n" as *u8) 98 sys_close(fd) 99 p("=== R4e WAIT RECON DONE ===\n" as *u8) 100 return 0 101}