nx_gpu_ring.nx

nx_gpu_ring.nx -- GATE: a GPU BAR/MMIO COMMAND-RING SUBMISSION MODEL (deepens GPU-DRIVER toward the real-hw BAR/ring gap). Where nx_gpu_driver has the vendor table + safe opcode set, THIS models the actual submission MECHANISM real GPUs use: a device with BAR-mapped MMIO registers (ring base/size/head/tail, doorbell, fence, status) over an mmap'd 'device memory', a command ring the host fills, a DOORBELL write that makes the device consume the ring, and a FENCE the device writes on completion that the host waits on. The rung before a real PCIe BAR submission. ★ NEVER-BRICK (cardinal 26) BY CONSTRUCTION: pure in-memory model over mmap'd 'BAR' memory -- touches NO real PCI device, NO firmware. The device's dispatch has ZERO firmware/vBIOS/flash-write opcodes and REFUSES (halts the ring, STATUS=ERR) any opcode outside the safe set -- the firmware-write path does not execute. The real-BAR activation (gpu_activate_real_bar) is REFUSED by construction. Proven mechanically in T4/T5, not asserted. T1 MMIO register read/write roundtrip (the BAR register file). T2 submit a frame: doorbell -> device consumes ring -> framebuffer reflects the commands -> fence signals completion (head advances to tail). T3 NEVER-BRICK: a normal frame has 0 firmware-write opcodes; the device runs it fully. T4 teeth: a firmware-write opcode in the ring is REFUSED -- device HALTS at it, fence not signalled, it never runs. T5 real-BAR activation refused by construction + determinism (process twice -> identical device memory). expect_exit: 0 Sovereign: nx_syscalls.