_gpu_bm_qmd_gate.nx

_gpu_bm_qmd_gate.nx -- BARE-METAL SOVEREIGN-GPU rung BM-GPU-C2: FAITHFUL Ampere+ compute QMD-by-pointer dispatch (hardens BM-GPU-C1's representative compute launch toward the real silicon dispatch). The real Ampere+ compute launch (NVC6C0, methods VERIFIED vs open spec clc6c0.h): bind the compute class (SET_OBJECT@0x0), write a QMD descriptor to memory, then SEND_PCAS_A@0x2b4 = QMD_GPU_VA>>8, then SEND_SIGNALING_PCAS2_B@0x2c0 with PCAS_ACTION INVALIDATE_COPY_SCHEDULE(=3)/SCHEDULE(=2) -> the SKED engine fetches the QMD and dispatches the grid. Kernel params live in a CONSTANT BUFFER (the real mechanism). The modeled SKED reads the QMD's const-buffer ptr, loads the GEMM params (A/B/C addrs + M/N/K), and runs the GEMM (SASS stand-in). NISHI-ECOSYSTEM-ONLY: our model+driver+command-stream. HONEST SCOPE: the LAUNCH METHOD SEQUENCE is FAITHFUL/verified (SET_OBJECT/SEND_PCAS_A/SEND_SIGNALING_PCAS2_B + the real PCAS_ACTION values); the QMD-INTERNAL field byte-offsets are REPRESENTATIVE (the QMDV0x bit-packing wasn't locatable in one fetch); the SKED+SASS execution STANDS IN. Real QMD layout + Blackwell sm_120 SASS GEMM kernel = BM-GPU-7 on real silicon. GREEN iff: after the faithful QMD dispatch, C == independent reference GEMM; AND tampers (no SEND_SIGNALING_PCAS2_B / PCAS_ACTION without SCHEDULE [NOP=0 or INVALIDATE-only=1]) leave C unwritten (the real SCHEDULE action is required). Marker -> knowledge/status/gpu_baremetal.log (BMQMDGATE). license_tier: ORIGINAL