_gpu_bm_qmd_gate.nx source

1// _gpu_bm_qmd_gate.nx -- BARE-METAL SOVEREIGN-GPU rung BM-GPU-C2: FAITHFUL Ampere+ compute QMD-by-pointer dispatch 2// (hardens BM-GPU-C1's representative compute launch toward the real silicon dispatch). 3// 4// The real Ampere+ compute launch (NVC6C0, methods VERIFIED vs open spec clc6c0.h): bind the compute class 5// (SET_OBJECT@0x0), write a QMD descriptor to memory, then SEND_PCAS_A@0x2b4 = QMD_GPU_VA>>8, then 6// SEND_SIGNALING_PCAS2_B@0x2c0 with PCAS_ACTION INVALIDATE_COPY_SCHEDULE(=3)/SCHEDULE(=2) -> the SKED engine fetches 7// the QMD and dispatches the grid. Kernel params live in a CONSTANT BUFFER (the real mechanism). The modeled SKED 8// reads the QMD's const-buffer ptr, loads the GEMM params (A/B/C addrs + M/N/K), and runs the GEMM (SASS stand-in). 9// 10// NISHI-ECOSYSTEM-ONLY: our model+driver+command-stream. HONEST SCOPE: the LAUNCH METHOD SEQUENCE is FAITHFUL/verified 11// (SET_OBJECT/SEND_PCAS_A/SEND_SIGNALING_PCAS2_B + the real PCAS_ACTION values); the QMD-INTERNAL field byte-offsets 12// are REPRESENTATIVE (the QMDV0x bit-packing wasn't locatable in one fetch); the SKED+SASS execution STANDS IN. Real 13// QMD layout + Blackwell sm_120 SASS GEMM kernel = BM-GPU-7 on real silicon. 14// 15// GREEN iff: after the faithful QMD dispatch, C == independent reference GEMM; AND tampers (no SEND_SIGNALING_PCAS2_B / 16// PCAS_ACTION without SCHEDULE [NOP=0 or INVALIDATE-only=1]) leave C unwritten (the real SCHEDULE action is required). 17// Marker -> knowledge/status/gpu_baremetal.log (BMQMDGATE). license_tier: ORIGINAL 18import "nx_syscalls.nx" 19 20const COMPUTE_CLASS: i64 = 0xCDC0 21const DIM: i64 = 4 22const SET_OBJECT: i64 = 0x0000 23const SEND_PCAS_A: i64 = 0x02b4 24const SEND_SIGNALING_PCAS2_B: i64 = 0x02c0 25const PCAS_ACTION_SCHEDULE: i64 = 0x2 26const PCAS_ACTION_INVALIDATE_COPY_SCHEDULE: i64 = 0x3 27 28func p(s: *u8) -> i64 { var nn: i64=0; while s[nn]!=(0 as u8){nn=nn+1} sys_write(1,s,nn); return 0 } 29func fp(fd: i64, s: *u8) -> i64 { var nn: i64=0; while s[nn]!=(0 as u8){nn=nn+1} sys_write(fd,s,nn); return 0 } 30func n(v: i64) -> i64 { let bb: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m;sys_write(1,"-" as *u8,1)}; let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48;k=1}; while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1}; var i: i64=0; while i<k{bb[i]=t[k-1-i];i=i+1}; sys_write(1,bb,k); return 0 } 31func x(v: i64) -> i64 { p("0x" as *u8); let bb:*u8=sys_mmap(20); var k:i64=0; var m:i64=v; if m==0{bb[0]=48;k=1}; while m>0{ let d:i64=m&15; if d<10{bb[k]=(48+d) as u8}else{bb[k]=(87+d) as u8}; m=(m>>4); k=k+1 } var i:i64=0; let o:*u8=sys_mmap(20); while i<k{o[i]=bb[k-1-i];i=i+1} sys_write(1,o,k); return 0 } 32func fx(fd: i64, v: i64) -> i64 { let bb:*u8=sys_mmap(20); var k:i64=0; var m:i64=v; if m==0{bb[0]=48;k=1}; while m>0{ let d:i64=m&15; if d<10{bb[k]=(48+d) as u8}else{bb[k]=(87+d) as u8}; m=(m>>4); k=k+1 } let o:*u8=sys_mmap(20); var i:i64=0; while i<k{o[i]=bb[k-1-i];i=i+1} fp(fd,"0x" as *u8); sys_write(fd,o,k); return 0 } 33func rd32(b: *u8, o: i64) -> i64 { return (b[o] as i64)|((b[o+1] as i64)<<8)|((b[o+2] as i64)<<16)|((b[o+3] as i64)<<24) } 34func wr32(b: *u8, o: i64, v: i64) -> i64 { b[o]=(v&0xff) as u8; b[o+1]=((v>>8)&0xff) as u8; b[o+2]=((v>>16)&0xff) as u8; b[o+3]=((v>>24)&0xff) as u8; return 0 } 35func rd64a(b: *u8, o: i64) -> i64 { return (rd32(b,o) & 0xffffffff) | (rd32(b,o+4) << 32) } 36 37// ===== FIFO/SKED model: faithful NVC6C0 QMD-by-pointer dispatch + GEMM (SASS stand-in) ===== 38// cs: [0]=qmd_addr [1]=bound_class 39func gpfifo_run_qmd(gmem: *u8, pb_off: i64, pb_dwords: i64, cs: *i64) -> i64 { 40 var i: i64 = 0 41 while i < pb_dwords { 42 let hdr: i64 = rd32(gmem, pb_off + i*4); i = i + 1 43 let mode: i64 = (hdr >> 29) & 0x7; let count: i64 = (hdr >> 16) & 0x1fff; let method0: i64 = (hdr & 0xfff) << 2 44 var j: i64 = 0 45 while j < count { 46 if i >= pb_dwords { j = count } else { 47 let data: i64 = rd32(gmem, pb_off + i*4); i = i + 1 48 var m: i64 = method0; if mode == 1 { m = method0 + j*4 } 49 if m == SET_OBJECT { cs[1] = data } 50 if cs[1] == COMPUTE_CLASS { 51 if m == SEND_PCAS_A { cs[0] = (data & 0xffffffff) << 8 } // QMD GPU VA (>>8 encoded) 52 if m == SEND_SIGNALING_PCAS2_B { 53 let action: i64 = data & 0x3 54 if (action == PCAS_ACTION_SCHEDULE) | (action == PCAS_ACTION_INVALIDATE_COPY_SCHEDULE) { 55 // SKED fetches the QMD -> const buffer -> GEMM params (representative QMD/cbuf layout) 56 let qmd: i64 = cs[0] 57 let cbuf: i64 = rd64a(gmem, qmd + 32) // QMD.constant_buffer_addr 58 let A: i64 = rd64a(gmem, cbuf + 0); let B: i64 = rd64a(gmem, cbuf + 8); let C: i64 = rd64a(gmem, cbuf + 16) 59 let M: i64 = rd32(gmem, cbuf + 24); let N: i64 = rd32(gmem, cbuf + 28); let K: i64 = rd32(gmem, cbuf + 32) 60 var ii: i64 = 0 61 while ii < M { var jj: i64 = 0 62 while jj < N { var sum: i64 = 0; var kk: i64 = 0 63 while kk < K { sum = sum + rd32(gmem, A+(ii*K+kk)*4) * rd32(gmem, B+(kk*N+jj)*4); kk=kk+1 } 64 wr32(gmem, C+(ii*N+jj)*4, sum); jj=jj+1 } 65 ii=ii+1 } 66 } 67 } 68 } 69 j = j + 1 70 } 71 } 72 } 73 return 0 74} 75func emit1(gmem: *u8, off: i64, subch: i64, method: i64, data: i64) -> i64 { 76 wr32(gmem, off, (1 << 29) | (1 << 16) | (subch << 13) | ((method >> 2) & 0xfff)); wr32(gmem, off+4, data); return 0 77} 78 79func main() -> i64 { 80 p("=== BARE-METAL SOVEREIGN-GPU BM-GPU-C2: faithful Ampere+ QMD-by-pointer compute dispatch + GEMM ===\n" as *u8) 81 let gmem: *u8 = sys_mmap(8388608) 82 let A: i64 = 0x10000; let B: i64 = 0x11000; let C: i64 = 0x12000 83 let QMD: i64 = 0x50000; let CBUF: i64 = 0x51000; let PB: i64 = 0x60000 // QMD 256-aligned 84 85 // fill A,B; reference GEMM 86 let refC: *i64 = sys_mmap(256) 87 var ii: i64 = 0 88 while ii < DIM { var kk: i64 = 0; while kk < DIM { wr32(gmem, A+(ii*DIM+kk)*4, ii+kk+1); kk=kk+1 } ii=ii+1 } 89 var kk2: i64 = 0; while kk2 < DIM { var jj: i64 = 0; while jj < DIM { wr32(gmem, B+(kk2*DIM+jj)*4, kk2+jj+2); jj=jj+1 } kk2=kk2+1 } 90 ii=0; while ii < DIM { var jj: i64 = 0; while jj < DIM { var s: i64 = 0; var k: i64 = 0; while k < DIM { s=s+(ii+k+1)*(k+jj+2); k=k+1 } refC[ii*DIM+jj]=s; jj=jj+1 } ii=ii+1 } 91 92 // build the CONSTANT BUFFER (kernel params: A,B,C addrs + M,N,K) 93 wr32(gmem, CBUF+0, A&0xffffffff); wr32(gmem, CBUF+4, (A>>32)&0xffffffff) 94 wr32(gmem, CBUF+8, B&0xffffffff); wr32(gmem, CBUF+12, (B>>32)&0xffffffff) 95 wr32(gmem, CBUF+16, C&0xffffffff); wr32(gmem, CBUF+20, (C>>32)&0xffffffff) 96 wr32(gmem, CBUF+24, DIM); wr32(gmem, CBUF+28, DIM); wr32(gmem, CBUF+32, DIM) 97 // build the QMD (program_addr@0, ..., constant_buffer_addr@32 [representative layout]) 98 wr32(gmem, QMD+0, 0x40000); wr32(gmem, QMD+4, 0) // program_address (the SASS GEMM kernel VA) 99 wr32(gmem, QMD+8, DIM); wr32(gmem, QMD+12, 1); wr32(gmem, QMD+16, 1) // grid dims 100 wr32(gmem, QMD+32, CBUF&0xffffffff); wr32(gmem, QMD+36, (CBUF>>32)&0xffffffff) // constant_buffer_addr 101 102 // ---- FAITHFUL launch pushbuffer: SET_OBJECT + SEND_PCAS_A(qmd>>8) + SEND_SIGNALING_PCAS2_B(INVALIDATE_COPY_SCHEDULE) ---- 103 var o: i64 = 0 104 emit1(gmem, PB+o, 1, SET_OBJECT, COMPUTE_CLASS); o=o+8 105 emit1(gmem, PB+o, 1, SEND_PCAS_A, QMD >> 8); o=o+8 106 emit1(gmem, PB+o, 1, SEND_SIGNALING_PCAS2_B, PCAS_ACTION_INVALIDATE_COPY_SCHEDULE); o=o+8 107 let cs: *i64 = sys_mmap(64); cs[1] = 0 108 gpfifo_run_qmd(gmem, PB, o/4, cs) 109 var matched: i64 = 1; var nz: i64 = 0; ii = 0 110 while ii < DIM*DIM { let cv: i64 = rd32(gmem, C+ii*4); if cv != refC[ii] { matched = 0 } if cv != 0 { nz = nz + 1 } ii=ii+1 } 111 p(" QMD dispatched (SEND_PCAS_A qmd>>8 + SIGNALING_PCAS2_B action=INVALIDATE_COPY_SCHEDULE). C[0,0]=" as *u8); n(rd32(gmem,C)); p(" ref=" as *u8); n(refC[0]); p(" C[3,3]=" as *u8); n(rd32(gmem,C+60)); p(" ref=" as *u8); n(refC[15]); p(" all_match=" as *u8); n(matched); p("\n" as *u8) 112 113 // ---- TAMPERS ---- 114 // T1: no SEND_SIGNALING_PCAS2_B (PCAS set but never scheduled) -> C unwritten 115 var z: i64 = 0; while z < DIM*DIM { wr32(gmem, C+z*4, 0); z=z+1 } 116 var o2: i64 = 0 117 emit1(gmem, PB+o2, 1, SET_OBJECT, COMPUTE_CLASS); o2=o2+8 118 emit1(gmem, PB+o2, 1, SEND_PCAS_A, QMD >> 8); o2=o2+8 119 let cs2: *i64 = sys_mmap(64); cs2[1]=0; gpfifo_run_qmd(gmem, PB, o2/4, cs2) 120 var t_nosched: i64 = 1; z=0; while z < DIM*DIM { if rd32(gmem, C+z*4) != 0 { t_nosched = 0 } z=z+1 } 121 // T2: SEND_SIGNALING_PCAS2_B with PCAS_ACTION INVALIDATE-only (=1, no SCHEDULE bit) -> not dispatched -> C unwritten 122 z=0; while z < DIM*DIM { wr32(gmem, C+z*4, 0); z=z+1 } 123 var o3: i64 = 0 124 emit1(gmem, PB+o3, 1, SET_OBJECT, COMPUTE_CLASS); o3=o3+8 125 emit1(gmem, PB+o3, 1, SEND_PCAS_A, QMD >> 8); o3=o3+8 126 emit1(gmem, PB+o3, 1, SEND_SIGNALING_PCAS2_B, 0x1); o3=o3+8 // INVALIDATE only 127 let cs3: *i64 = sys_mmap(64); cs3[1]=0; gpfifo_run_qmd(gmem, PB, o3/4, cs3) 128 var t_noschedule_action: i64 = 1; z=0; while z < DIM*DIM { if rd32(gmem, C+z*4) != 0 { t_noschedule_action = 0 } z=z+1 } 129 p(" [tamper] no-SIGNALING_PCAS2_B C-unwritten=" as *u8); n(t_nosched); p(" action-INVALIDATE-only(no-schedule) C-unwritten=" as *u8); n(t_noschedule_action); p("\n" as *u8) 130 131 var pass: i64 = 0 132 if matched == 1 { if nz == DIM*DIM { if t_nosched == 1 { if t_noschedule_action == 1 { pass = 1 } } } } 133 p(" checks: gemm_matches_ref=" as *u8); n(matched); p(" all16_nonzero=" as *u8); n(nz==16); p(" schedule-method-required=" as *u8); n(t_nosched); p(" SCHEDULE-action-required=" as *u8); n(t_noschedule_action); p("\n" as *u8) 134 135 let lfd: i64 = sys_openat_append("knowledge/status/gpu_baremetal.log" as *u8, 0x1a4) 136 if pass == 1 { 137 p("BMQMDGATE verdict=GREEN reason=FAITHFUL-Ampere+-QMD-by-pointer-compute-dispatch (VERIFIED methods SET_OBJECT@0x0 + SEND_PCAS_A@0x2b4[qmd>>8] + SEND_SIGNALING_PCAS2_B@0x2c0[PCAS_ACTION INVALIDATE_COPY_SCHEDULE=3]; kernel params in a CONSTANT BUFFER; modeled SKED fetches QMD->cbuf->runs 4x4 GEMM, C matches ref; tampers no-schedule-method + action-without-SCHEDULE leave C unwritten) SCOPE=LAUNCH-METHODS-FAITHFUL[verified],QMD-internal-offsets-representative,SKED+SASS-stand-in; real-QMD-layout+Blackwell-SASS=BM-GPU-7\n" as *u8) 138 if lfd >= 0 { 139 fp(lfd, "BMQMDGATE verdict=GREEN rung=BM-GPU-C2-qmd-dispatch device=sovereign-NVC6C0-QMD-model launch=SET_OBJECT+SEND_PCAS_A@0x2b4+SEND_SIGNALING_PCAS2_B@0x2c0(action=INVALIDATE_COPY_SCHEDULE=3)[VERIFIED] params-in-const-buffer gemm=4x4 C[0,0]=" as *u8); fx(lfd, rd32(gmem,C)) 140 fp(lfd, " matches_ref=1 tampers=held(no-schedule-method+action-no-SCHEDULE->C-unwritten) HARDENS-C1(launch-methods-now-FAITHFUL) scope=launch-faithful/QMD-offsets-representative/SKED+SASS-stand-in next=BM-GPU-7-real-QMD-layout+Blackwell-SASS / BM-GPU-6-real-silicon\n" as *u8) 141 sys_close(lfd) 142 } 143 sys_exit(0); return 0 144 } 145 p("BMQMDGATE verdict=RED (gemm mismatch or tamper not satisfied)\n" as *u8) 146 if lfd >= 0 { fp(lfd, "BMQMDGATE verdict=RED see-console\n" as *u8); sys_close(lfd) } 147 sys_exit(1) 148 return 1 149}