_gpu_dxg_mapva_gate.nx

_gpu_dxg_mapva_gate.nx -- SOVEREIGN-GPU ladder R4e (map a real allocation to a GPU VIRTUAL ADDRESS on the 5080). The keystone uniting R4c (paging queue + fence page) and R4d (allocation): LX_DXMAPGPUVIRTUALADDRESS assigns the allocation a GPU virtual address (synchronously) and pages it in ASYNC -> completion is signaled when the paging queue's monitored fence reaches the returned paging_fence_value. We WAIT by polling the kernel-mapped fence page (R4c) -> proves the GPU actually completed the mapping. ABI (header-derived, natural-aligned, recon-confirmed live): LX_DXMAPGPUVIRTUALADDRESS = 0xC068470C (size 104). d3dddi_mapgpuvirtualaddress: paging_queue@0; base_address@8(=0 auto); minimum_address@16; maximum_address@24; allocation@32; offset_in_pages@40; size_in_pages@48; protection@56 (write=bit0); driver_protection@64; virtual_address@88 (OUT); paging_fence_value@96 (OUT). ret=259 = STATUS_PENDING (accepted, async). GREEN iff (author=organ, from REAL device returns): A) chain ok (device + paging queue [capture fence_cpu_va] + EXISTINGHEAP allocation); B) MAP #1 ret==STATUS_PENDING(259) AND gpu_va != 0 AND paging_fence_value > fence-before; C) the paging fence ADVANCES to paging_fence_value (poll the kernel fence page) = GPU completed the map; D) MAP #2 ret pending AND gpu_va2 != 0 AND gpu_va2 != gpu_va1 (distinct real VAs) AND its fence also completes; E) TAMPER: T1 bogus paging_queue(0xdeadbeef) -> negative errno; T2 bogus allocation -> negative; T3 non-dxg fd -> -ENOTTY. Marker -> knowledge/status/gpu_dxg.log (DXGMAPGATE). raw syscalls only. NO-WAVE: assigns + pages-in a GPU VA (real memory addressing); NO compute/throughput (that is R7). ZERO speedup claimed. license_tier: ORIGINAL