code wiki / _hdl_build / nx_gpu_driver.nx

nx_gpu_driver.nx

buildroot/runtime/_hdl_build/nx_gpu_driver.nx

7197 B84 linesdepth 3pulls 4 transitivereach 0 importersview sourcekind tooltopic gpu
docsdependenciesstructsconstsfunctions

about

nx_gpu_driver.nx -- SOVEREIGN UNIVERSAL GPU-DRIVER FRAMEWORK (operator: "not just our own gpu driver but all of them"). Vendor-parameterized: a PCI vendor table (NVIDIA/AMD/Intel = real vendor IDs) + a command-ring model built from a SAFE opcode set (clear/draw/copy/compute/fence-read ONLY) + a submit path. Grounded on the OPEN driver path (gd_*.raw: foss/nouveau/mesa/drm/pcie/intel) -> drive vendor GPUs WITHOUT the proprietary stack/DirectX. ★ CARDINAL 26 NEVER-BRICK BY CONSTRUCTION (proven, not asserted): the opcode whitelist contains ZERO firmware/ vBIOS/EEPROM-write ops; the submit path REFUSES any opcode outside it. A GPU driver writes hardware -- this is exactly where one brick kills the brand, so the firmware-write path simply DOES NOT EXIST here. T1 NVIDIA/AMD/Intel recognized by PCI vendor ID (unknown rejected). T2 a frame command-ring builds + submits. T3 NEVER-BRICK -- a normal frame has 0 firmware-write opcodes. T4 (teeth) a firmware-write opcode is REFUSED. HONEST: framework + safe-submission MODEL; real-hardware BAR/ring submission = the guarded next step (real GPU + PCI). expect_exit: 0 Sovereign: nx_syscalls.

dependencies 3 imports · 0 importers

nx_syscalls.nx nx_itoa_lib.nx nx_g_puts_lib.nx nx_gpu_driver.nx

imports: nx_syscalls.nxnx_itoa_lib.nxnx_g_puts_lib.nx

imported by: nobody (leaf or entry point)

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

main g_puts sys_write g_hex g_puts ↻ sys_mmap sys_write ↻ g_pn nxi_out nxi_fd sys_mmap ↻ ccz_cat_num sys_write ↻ sys_munmap vendor_idx vendor_name ck g_puts ↻ sys_mmap ↻ build_frame submit_ring op_is_safe count_unsafe op_is_safe ↻ op_is_safe ↻ sys_openat_append sys_write ↻ sys_close sys_exit

structs

none

consts

25const OP_CLEAR: i64 = 1
26const OP_DRAW: i64 = 2
27const OP_COPY: i64 = 3
28const OP_COMPUTE: i64 = 4
29const OP_FENCE: i64 = 5 // read completion (no write)
30const OP_FW_WRITE: i64 = 100 // firmware write -- the brick risk; NOT in the safe set, used only to PROVE refusal

functions

20func g_pn(v: i64) -> i64 { nxi_out(v); return 0 }
called by 1: main calls 1: nxi_out
21func g_hex(v: i64) -> i64 { g_puts("0x" as *u8); let b: *u8=sys_mmap(16); var i: i64=3; var k: i64=0; while i>=0 { let nib: i64=(v>>(i*4))&15; if nib<10 { b[k]=(48+nib) as u8 } else { b[k]=(55+nib) as u8 } k=k+1; i=i-1 } sys_write(1,b,4); return 0 }
called by 1: main calls 3: g_putssys_mmapsys_write
22func ck(name: *u8, c: i64) -> i64 { if c==1 { g_puts(" PASS " as *u8) } else { g_puts(" FAIL " as *u8) } g_puts(name); g_puts("\n" as *u8); return c }
called by 1: main calls 1: g_puts
31func op_is_safe(op: i64) -> i64 { if op>=1 { if op<=5 { return 1 } } return 0 }
34func vendor_idx(id: i64) -> i64 { if id==0x10DE { return 0 } if id==0x1002 { return 1 } if id==0x8086 { return 2 } return 0-1 }
called by 1: main
35func vendor_name(idx: i64) -> *u8 { if idx==0 { return "NVIDIA" as *u8 } if idx==1 { return "AMD " as *u8 } if idx==2 { return "Intel " as *u8 } return "UNKNOWN" as *u8 }
called by 1: main
38func build_frame(ring: *i64) -> i64 { ring[0]=OP_CLEAR; ring[1]=0; ring[2]=OP_DRAW; ring[3]=100; ring[4]=OP_DRAW; ring[5]=50; ring[6]=OP_FENCE; ring[7]=0; return 4 }
called by 1: main
40func submit_ring(ring: *i64, n: i64) -> i64 { var i: i64=0; while i<n { if op_is_safe(ring[2*i])==0 { return 0-1 } i=i+1 } return n }
called by 1: main calls 1: op_is_safe
41func count_unsafe(ring: *i64, n: i64) -> i64 { var c: i64=0; var i: i64=0; while i<n { if op_is_safe(ring[2*i])==0 { c=c+1 } i=i+1 } return c }
called by 1: main calls 1: op_is_safe
43func main() -> i64