nx_gpu_driver.nx source

1// nx_gpu_driver.nx -- SOVEREIGN UNIVERSAL GPU-DRIVER FRAMEWORK (operator: "not just our own gpu driver but all of 2// them"). Vendor-parameterized: a PCI vendor table (NVIDIA/AMD/Intel = real vendor IDs) + a command-ring model 3// built from a SAFE opcode set (clear/draw/copy/compute/fence-read ONLY) + a submit path. Grounded on the OPEN 4// driver path (gd_*.raw: foss/nouveau/mesa/drm/pcie/intel) -> drive vendor GPUs WITHOUT the proprietary stack/DirectX. 5// ★ CARDINAL 26 NEVER-BRICK BY CONSTRUCTION (proven, not asserted): the opcode whitelist contains ZERO firmware/ 6// vBIOS/EEPROM-write ops; the submit path REFUSES any opcode outside it. A GPU driver writes hardware -- this is 7// exactly where one brick kills the brand, so the firmware-write path simply DOES NOT EXIST here. 8// T1 NVIDIA/AMD/Intel recognized by PCI vendor ID (unknown rejected). T2 a frame command-ring builds + submits. 9// T3 NEVER-BRICK -- a normal frame has 0 firmware-write opcodes. T4 (teeth) a firmware-write opcode is REFUSED. 10// HONEST: framework + safe-submission MODEL; real-hardware BAR/ring submission = the guarded next step (real GPU + PCI). 11// expect_exit: 0 Sovereign: nx_syscalls. 12import "nx_syscalls.nx" 13import "nx_itoa_lib.nx" // shared MSB-first emitter (zero-alloc) 14import "nx_g_puts_lib.nx" 15 16// MIGRATED to the shared emitter (debt 1785563586). The old body mmapped a scratch buffer 17// per call and never freed it. At PAGE granularity that is 4096B leaked PER CALL -- the 18// defect that took 28.5GB of a 36GB host in nx_ts_lumadiff (2MB input, ~3.66M calls). 19// nxi_* is MSB-first, allocates NOTHING, and emits identical bytes including the sign. 20func g_pn(v: i64) -> i64 { nxi_out(v); return 0 } 21func g_hex(v: i64) -> i64 { g_puts("0x" as *u8); let b: *u8=sys_mmap(16); var i: i64=3; var k: i64=0; while i>=0 { let nib: i64=(v>>(i*4))&15; if nib<10 { b[k]=(48+nib) as u8 } else { b[k]=(55+nib) as u8 } k=k+1; i=i-1 } sys_write(1,b,4); return 0 } 22func ck(name: *u8, c: i64) -> i64 { if c==1 { g_puts(" PASS " as *u8) } else { g_puts(" FAIL " as *u8) } g_puts(name); g_puts("\n" as *u8); return c } 23 24// the SAFE opcode set (command-submission + read ONLY). Firmware/vBIOS/EEPROM-write opcodes are DELIBERATELY ABSENT. 25const OP_CLEAR: i64 = 1 26const OP_DRAW: i64 = 2 27const OP_COPY: i64 = 3 28const OP_COMPUTE: i64 = 4 29const OP_FENCE: i64 = 5 // read completion (no write) 30const OP_FW_WRITE: i64 = 100 // firmware write -- the brick risk; NOT in the safe set, used only to PROVE refusal 31func op_is_safe(op: i64) -> i64 { if op>=1 { if op<=5 { return 1 } } return 0 } 32 33// PCI vendor table (real vendor IDs) -- vendor is a DATA param => the framework covers ALL GPUs. 34func vendor_idx(id: i64) -> i64 { if id==0x10DE { return 0 } if id==0x1002 { return 1 } if id==0x8086 { return 2 } return 0-1 } 35func vendor_name(idx: i64) -> *u8 { if idx==0 { return "NVIDIA" as *u8 } if idx==1 { return "AMD " as *u8 } if idx==2 { return "Intel " as *u8 } return "UNKNOWN" as *u8 } 36 37// command ring: ring[2*i]=opcode, ring[2*i+1]=arg. A typical frame: clear -> draw -> draw -> fence. 38func build_frame(ring: *i64) -> i64 { ring[0]=OP_CLEAR; ring[1]=0; ring[2]=OP_DRAW; ring[3]=100; ring[4]=OP_DRAW; ring[5]=50; ring[6]=OP_FENCE; ring[7]=0; return 4 } 39// submit: validate EVERY opcode is in the safe set (the never-brick guard) before submission; refuse the whole ring otherwise. 40func submit_ring(ring: *i64, n: i64) -> i64 { var i: i64=0; while i<n { if op_is_safe(ring[2*i])==0 { return 0-1 } i=i+1 } return n } 41func count_unsafe(ring: *i64, n: i64) -> i64 { var c: i64=0; var i: i64=0; while i<n { if op_is_safe(ring[2*i])==0 { c=c+1 } i=i+1 } return c } 42 43func main() -> i64 { 44 g_puts("nx_gpu_driver (SOVEREIGN universal GPU-driver framework: NVIDIA/AMD/Intel; NEVER-BRICK by construction)\n" as *u8) 45 var pass: i64=0; var total: i64=0 46 47 g_puts(" -- vendor coverage (PCI vendor ID -> driver, vendor is a DATA param = ALL GPUs) --\n" as *u8) 48 g_puts(" NVIDIA="); g_hex(0x10DE); g_puts(" -> idx "); g_pn(vendor_idx(0x10DE)); g_puts(" ("); g_puts(vendor_name(vendor_idx(0x10DE))); g_puts(")\n" as *u8) 49 g_puts(" AMD ="); g_hex(0x1002); g_puts(" -> idx "); g_pn(vendor_idx(0x1002)); g_puts(" ("); g_puts(vendor_name(vendor_idx(0x1002))); g_puts(")\n" as *u8) 50 g_puts(" Intel ="); g_hex(0x8086); g_puts(" -> idx "); g_pn(vendor_idx(0x8086)); g_puts(" ("); g_puts(vendor_name(vendor_idx(0x8086))); g_puts(")\n" as *u8) 51 var t1: i64=0; if vendor_idx(0x10DE)==0 { if vendor_idx(0x1002)==1 { if vendor_idx(0x8086)==2 { if vendor_idx(0xFFFF)==(0-1) { t1=1 } } } } 52 pass=pass+ck("T1: NVIDIA/AMD/Intel recognized by real PCI vendor ID; an unknown vendor is rejected (teeth)" as *u8, t1); total=total+1 53 54 let ring: *i64 = sys_mmap(64*8) as *i64 55 let n: i64 = build_frame(ring) 56 let sub: i64 = submit_ring(ring, n) 57 g_puts(" frame built: "); g_pn(n); g_puts(" commands (clear/draw/draw/fence); submit_ring="); g_pn(sub); g_puts("\n" as *u8) 58 var t2: i64=0; if n==4 { if sub==4 { t2=1 } } 59 pass=pass+ck("T2: a frame command-ring builds (safe ops) and the submit path accepts it" as *u8, t2); total=total+1 60 61 let unsafe_n: i64 = count_unsafe(ring, n) 62 g_puts(" NEVER-BRICK SCAN of the frame: firmware/vBIOS/EEPROM-write opcodes = "); g_pn(unsafe_n); g_puts(" (MUST be 0)\n" as *u8) 63 var t3: i64=0; if unsafe_n==0 { t3=1 } 64 pass=pass+ck("T3 (NEVER-BRICK, cardinal 26): a normal frame contains 0 firmware-write opcodes -- the write path does not exist" as *u8, t3); total=total+1 65 66 // T4 teeth: try to submit a firmware-write opcode -> the guard REFUSES it (proven, not asserted) 67 let bad: *i64 = sys_mmap(8*8) as *i64; bad[0]=OP_CLEAR; bad[1]=0; bad[2]=OP_FW_WRITE; bad[3]=0xDEAD 68 let badsub: i64 = submit_ring(bad, 2) 69 g_puts(" attempted a ring with a firmware-WRITE opcode (OP_FW_WRITE=100): submit_ring="); g_pn(badsub); g_puts(" (-1 = REFUSED)\n" as *u8) 70 var t4: i64=0; if op_is_safe(OP_FW_WRITE)==0 { if badsub==(0-1) { t4=1 } } 71 pass=pass+ck("T4 (teeth): a firmware-write opcode is REFUSED by the submit guard -- never-brick proven mechanically" as *u8, t4); total=total+1 72 73 g_puts(" -- the sovereign open-driver path (grounded gd_*.raw): foss/nouveau(NVIDIA)/mesa/drm-kms/pcie/intel --\n" as *u8) 74 g_puts(" HONEST: this is the vendor framework + SAFE-submission model; real-hardware BAR/ring submission on a live GPU = the guarded next step.\n" as *u8) 75 76 var okall: i64=0; if pass==total { okall=1 } 77 g_puts("---- nx_gpu_driver: passed "); g_pn(pass); g_puts(" / "); g_pn(total); g_puts(" ----\n" as *u8) 78 if okall==1 { 79 let logf: i64=sys_openat_append("knowledge/status/gpu_driver.log" as *u8, 420) 80 if logf>=0 { let z: i64=sys_write(logf,"NXGPUDRIVER GREEN: universal vendor framework (NVIDIA/AMD/Intel); NEVER-BRICK by construction (0 fw-write opcodes; fw-write refused)\n" as *u8,127); sys_close(logf) } 81 g_puts("verdict=GREEN (sovereign universal GPU-driver framework: all vendors by PCI ID; NEVER-BRICK by construction -- firmware-write path does not exist + is refused)\n" as *u8); sys_exit(0); return 0 82 } 83 g_puts("verdict=RED\n" as *u8); sys_exit(1); return 1 84}