_gpu_bm_pci_gate.nx source

1// _gpu_bm_pci_gate.nx -- BARE-METAL SOVEREIGN-GPU rung BM-GPU-2: PCIe config-space enumeration + GPU identify + 2// BAR decode against a spec-faithful sovereign PCIe config model. 3// 4// A sovereign driver parses the standard PCIe config space (last-mile hardware spec): vendor/device @0x00/0x02, 5// class code @0x0B/0x0A, BAR0 @0x10 (MMIO, with the real WRITE-1s SIZE-DISCOVERY behavior), BAR1 @0x14/0x18 6// (64-bit prefetchable VRAM aperture). It identifies an NVIDIA discrete GPU (vendor 0x10DE, base-class 0x03=display) 7// and decodes BAR base+size. This is the EXACT logic that runs against real /sys/bus/pci/config or ECAM at BM-GPU-6. 8// NISHI-ECOSYSTEM-ONLY: our model + our driver; PCIe config layout = the last-mile hardware spec. 9// HONEST SCOPE: enumeration LOGIC vs a spec-faithful model; the model's device-id (0x2C02) is a Blackwell-representative 10// placeholder -- the REAL 5080 id is read from real hardware at BM-GPU-6. NO real silicon. 11// 12// GREEN iff: vendor==0x10DE (NVIDIA), base-class==0x03 (display=GPU), BAR0 is memory-space w/ base!=0 and size 13// discovered ==16MiB (faithful write-1s sizing), BAR1 decoded as 64-bit prefetchable w/ base!=0; AND tampers 14// (Intel vendor / network class / BAR0 IO-space bit) are correctly REJECTED/flagged by the driver. 15// Marker -> knowledge/status/gpu_baremetal.log (BMPCIGATE). license_tier: ORIGINAL 16import "nx_syscalls.nx" 17 18func p(s: *u8) -> i64 { var nn: i64=0; while s[nn]!=(0 as u8){nn=nn+1} sys_write(1,s,nn); return 0 } 19func fp(fd: i64, s: *u8) -> i64 { var nn: i64=0; while s[nn]!=(0 as u8){nn=nn+1} sys_write(fd,s,nn); return 0 } 20func n(v: i64) -> i64 { let bb: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m;sys_write(1,"-" as *u8,1)}; let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48;k=1}; while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1}; var i: i64=0; while i<k{bb[i]=t[k-1-i];i=i+1}; sys_write(1,bb,k); return 0 } 21func x(v: i64) -> i64 { p("0x" as *u8); let bb:*u8=sys_mmap(20); var k:i64=0; var m:i64=v; if m==0{bb[0]=48;k=1}; while m>0{ let d:i64=m&15; if d<10{bb[k]=(48+d) as u8}else{bb[k]=(87+d) as u8}; m=(m>>4); k=k+1 } var i:i64=0; let o:*u8=sys_mmap(20); while i<k{o[i]=bb[k-1-i];i=i+1} sys_write(1,o,k); return 0 } 22func fx(fd: i64, v: i64) -> i64 { let bb:*u8=sys_mmap(20); var k:i64=0; var m:i64=v; if m==0{bb[0]=48;k=1}; while m>0{ let d:i64=m&15; if d<10{bb[k]=(48+d) as u8}else{bb[k]=(87+d) as u8}; m=(m>>4); k=k+1 } let o:*u8=sys_mmap(20); var i:i64=0; while i<k{o[i]=bb[k-1-i];i=i+1} fp(fd,"0x" as *u8); sys_write(fd,o,k); return 0 } 23func rd16(b: *u8, o: i64) -> i64 { return (b[o] as i64)|((b[o+1] as i64)<<8) } 24func rd32(b: *u8, o: i64) -> i64 { return (b[o] as i64)|((b[o+1] as i64)<<8)|((b[o+2] as i64)<<16)|((b[o+3] as i64)<<24) } 25func wr16(b: *u8, o: i64, v: i64) -> i64 { b[o]=(v&0xff) as u8; b[o+1]=((v>>8)&0xff) as u8; return 0 } 26func wr32(b: *u8, o: i64, v: i64) -> i64 { b[o]=(v&0xff) as u8; b[o+1]=((v>>8)&0xff) as u8; b[o+2]=((v>>16)&0xff) as u8; b[o+3]=((v>>24)&0xff) as u8; return 0 } 27 28// ===== sovereign PCIe config-space MODEL with faithful BAR0 size-discovery ===== 29// BAR0 write applies a write-mask + type bits (real PCIe: address bits are writable, alignment/type bits are RO), 30// so writing 0xFFFFFFFF then reading back returns the size mask -> the driver derives the BAR size, exactly as on HW. 31const BAR0_WRITEMASK: i64 = 0xFF000000 // 16 MiB region: bits 31:24 writable 32const BAR0_TYPEBITS: i64 = 0x0 // memory space (bit0=0), 32-bit (bits2:1=00), non-prefetchable (bit3=0) 33func model_write_bar0(cfg: *u8, val: i64) -> i64 { wr32(cfg, 0x10, (val & BAR0_WRITEMASK) | BAR0_TYPEBITS); return 0 } 34 35// build a spec-faithful NVIDIA-GPU config space. `vendor`,`baseclass`,`bar0_io` let tampers vary key fields. 36func build_cfg(cfg: *u8, vendor: i64, baseclass: i64, bar0_io: i64) -> i64 { 37 var z: i64 = 0; while z < 256 { cfg[z] = 0 as u8; z = z + 1 } 38 wr16(cfg, 0x00, vendor); wr16(cfg, 0x02, 0x2C02) // vendor ; device-id (Blackwell GB203 placeholder) 39 wr16(cfg, 0x04, 0x0007); wr16(cfg, 0x06, 0x0010) // command(IO+mem+busmaster) ; status(cap list) 40 cfg[0x08] = 0xA1 as u8 // revision 41 cfg[0x09] = 0x00 as u8; cfg[0x0A] = 0x00 as u8; cfg[0x0B] = (baseclass & 0xff) as u8 // prog-if/subclass/base-class 42 cfg[0x0E] = 0x00 as u8 // header type = 0 (endpoint) 43 var b0: i64 = 0xFB000000 | BAR0_TYPEBITS // BAR0 = 16MiB MMIO @0xFB000000 44 if bar0_io == 1 { b0 = b0 | 0x1 } // tamper: set IO-space bit 45 wr32(cfg, 0x10, b0) 46 wr32(cfg, 0x14, 0x0000000C) // BAR1 low: base 0x6_00000000, 64-bit(bits2:1=10)+pref(bit3=1) 47 wr32(cfg, 0x18, 0x00000006) // BAR1 high 48 wr16(cfg, 0x2C, 0x10DE); wr16(cfg, 0x2E, 0x2C02) // subsystem vendor/id 49 cfg[0x34] = 0x40 as u8 // capabilities pointer 50 cfg[0x3D] = 0x01 as u8 // interrupt pin A 51 return 0 52} 53 54// the sovereign DRIVER: enumerate one config space. writes [is_nvidia, is_gpu, bar0_is_mem, bar0_base, bar0_size, bar1_64, bar1_pref, bar1_base_lo] into out[]. 55func enumerate(cfg: *u8, out: *i64) -> i64 { 56 let vendor: i64 = rd16(cfg, 0x00); let device: i64 = rd16(cfg, 0x02) 57 let baseclass: i64 = cfg[0x0B] as i64 58 // BAR0 base + size discovery (write 0xFFFFFFFF, read mask, restore) 59 let bar0_orig: i64 = rd32(cfg, 0x10) 60 model_write_bar0(cfg, 0xFFFFFFFF); let bar0_mask: i64 = rd32(cfg, 0x10); model_write_bar0(cfg, bar0_orig) 61 let bar0_is_mem: i64 = 1 - (bar0_orig & 1) 62 let bar0_base: i64 = bar0_orig & 0xFFFFFFF0 63 let bar0_size: i64 = ((bar0_mask & 0xFFFFFFF0) ^ 0xFFFFFFF0) + 16 // ~mask(addr bits)+1, +16 covers the masked low nibble 64 // BAR1 64-bit prefetchable decode 65 let bar1_lo: i64 = rd32(cfg, 0x14); let bar1_hi: i64 = rd32(cfg, 0x18) 66 let bar1_64: i64 = 0; if ((bar1_lo >> 1) & 3) == 2 { out[8] = 1 } 67 out[0] = vendor; out[1] = baseclass 68 out[2] = bar0_is_mem; out[3] = bar0_base; out[4] = bar0_size 69 if ((bar1_lo >> 1) & 3) == 2 { out[5] = 1 } else { out[5] = 0 } 70 out[6] = (bar1_lo >> 3) & 1 71 out[7] = (bar1_lo & 0xFFFFFFF0) | (bar1_hi << 32) 72 out[9] = device 73 return 0 74} 75 76func main() -> i64 { 77 p("=== BARE-METAL SOVEREIGN-GPU BM-GPU-2: PCIe config enum + identify the NVIDIA GPU + decode BARs ===\n" as *u8) 78 let cfg: *u8 = sys_mmap(256) 79 let o: *i64 = sys_mmap(128) 80 81 build_cfg(cfg, 0x10DE, 0x03, 0); enumerate(cfg, o) 82 let vendor: i64 = o[0]; let bclass: i64 = o[1]; let bar0_mem: i64 = o[2]; let bar0_base: i64 = o[3]; let bar0_size: i64 = o[4] 83 let bar1_64: i64 = o[5]; let bar1_pref: i64 = o[6]; let bar1_base: i64 = o[7]; let device: i64 = o[9] 84 var is_nvidia: i64 = 0; if vendor == 0x10DE { is_nvidia = 1 } 85 var is_gpu: i64 = 0; if bclass == 0x03 { is_gpu = 1 } 86 p(" vendor=" as *u8); x(vendor); p(" device=" as *u8); x(device); p(" base_class=" as *u8); x(bclass) 87 p(" -> NVIDIA=" as *u8); n(is_nvidia); p(" GPU=" as *u8); n(is_gpu); p("\n" as *u8) 88 p(" BAR0 mem=" as *u8); n(bar0_mem); p(" base=" as *u8); x(bar0_base); p(" size=" as *u8); x(bar0_size); p(" (=" as *u8); n(bar0_size/1048576); p("MiB)\n" as *u8) 89 p(" BAR1 64bit=" as *u8); n(bar1_64); p(" prefetch=" as *u8); n(bar1_pref); p(" base=" as *u8); x(bar1_base); p("\n" as *u8) 90 91 // ---- TAMPERS: the driver must NOT mis-identify ---- 92 let c2: *u8 = sys_mmap(256); let o2: *i64 = sys_mmap(128) 93 build_cfg(c2, 0x8086, 0x03, 0); enumerate(c2, o2); var t_intel: i64 = 0; if o2[0] != 0x10DE { t_intel = 1 } // Intel vendor -> not-NVIDIA 94 let c3: *u8 = sys_mmap(256); let o3: *i64 = sys_mmap(128) 95 build_cfg(c3, 0x10DE, 0x02, 0); enumerate(c3, o3); var t_net: i64 = 0; if o3[1] != 0x03 { t_net = 1 } // network class -> not-GPU 96 let c4: *u8 = sys_mmap(256); let o4: *i64 = sys_mmap(128) 97 build_cfg(c4, 0x10DE, 0x03, 1); enumerate(c4, o4); var t_io: i64 = 0; if o4[2] == 0 { t_io = 1 } // BAR0 IO-space bit -> not-mem flagged 98 p(" [tamper] intel-vendor-rejected=" as *u8); n(t_intel); p(" net-class-rejected=" as *u8); n(t_net); p(" bar0-io-flagged=" as *u8); n(t_io); p("\n" as *u8) 99 100 var pass: i64 = 0 101 if is_nvidia == 1 { if is_gpu == 1 { if bar0_mem == 1 { if bar0_base != 0 { if bar0_size == 0x1000000 { 102 if bar1_64 == 1 { if bar1_pref == 1 { if bar1_base != 0 { if t_intel == 1 { if t_net == 1 { if t_io == 1 { pass = 1 } } } } } } } } } } } 103 p(" checks: nvidia=" as *u8); n(is_nvidia); p(" gpu=" as *u8); n(is_gpu); p(" bar0_16MiB=" as *u8); n(bar0_size==0x1000000); p(" bar1_64bit_pref=" as *u8); var b: i64=0; if bar1_64==1 { if bar1_pref==1 { b=1 } } n(b); p(" tampers_ok=" as *u8); var tk: i64=0; if t_intel==1 { if t_net==1 { if t_io==1 { tk=1 } } } n(tk); p("\n" as *u8) 104 105 let lfd: i64 = sys_openat_append("knowledge/status/gpu_baremetal.log" as *u8, 0x1a4) 106 if pass == 1 { 107 p("BMPCIGATE verdict=GREEN reason=sovereign-driver-enumerates-PCIe-config+identifies-NVIDIA-GPU(0x10DE,class0x03)+decodes-BAR0(16MiB-MMIO,faithful-write-1s-size-discovery)+BAR1(64bit-prefetchable-VRAM-aperture); tampers intel-vendor/net-class/BAR0-IO-bit all correctly rejected SCOPE=enum-LOGIC-vs-spec-model-NOT-real-silicon; real=/sys/bus/pci|ECAM at BM-GPU-6\n" as *u8) 108 if lfd >= 0 { 109 fp(lfd, "BMPCIGATE verdict=GREEN rung=BM-GPU-2-pcie-enum device=sovereign-NVIDIA-PCIe-model vendor=" as *u8); fx(lfd, vendor) 110 fp(lfd, " device_id=" as *u8); fx(lfd, device); fp(lfd, "(model-placeholder) base_class=0x03 BAR0_base=" as *u8); fx(lfd, bar0_base) 111 fp(lfd, " BAR0_size=" as *u8); fx(lfd, bar0_size); fp(lfd, " BAR1_64bit_pref_base=" as *u8); fx(lfd, bar1_base) 112 fp(lfd, " tampers=rejected(intel-vendor+net-class+bar0-io-bit) scope=enum-logic-vs-spec-model-NOT-real-silicon next=BM-GPU-3-BAR0-boot-regs; real-enum=/sys/bus/pci|ECAM on native Linux\n" as *u8) 113 sys_close(lfd) 114 } 115 sys_exit(0); return 0 116 } 117 p("BMPCIGATE verdict=RED (identify/BAR-decode/tamper not satisfied)\n" as *u8) 118 if lfd >= 0 { fp(lfd, "BMPCIGATE verdict=RED see-console\n" as *u8); sys_close(lfd) } 119 sys_exit(1) 120 return 1 121}