_gpu_dxg_makeresident_gate.nx source

1// _gpu_dxg_makeresident_gate.nx -- SOVEREIGN-GPU ladder R4f (make a real allocation GPU-RESIDENT on the 5080). 2// 3// After R4d (allocate) + R4e (map to GPU VA), R4f pins the allocation's pages into GPU-accessible memory via 4// LX_DXMAKERESIDENT -- the last residency step before command submission can touch it. Async like map: 5// completion is signaled when the paging queue's monitored fence reaches paging_fence_value (poll the R4c page). 6// 7// ABI (header-derived, recon-confirmed): LX_DXMAKERESIDENT = 0xC030470B (size 48). d3dddi_makeresident: 8// paging_queue@0; alloc_count@4; allocation_list@8 (ptr->array of d3dkmthandle); priority_list@16 (ptr->array 9// of u32); flags@24; paging_fence_value@32 (OUT); num_bytes_to_trim@40 (OUT). ret=259 STATUS_PENDING on a fresh 10// allocation (then fence advances); a 2nd makeresident on the SAME alloc returns 0 (already resident). 11// 12// GREEN iff (author=organ, from REAL device returns): 13// A) chain ok (device + paging queue [capture fence_cpu_va]); 14// B) alloc #1 (fresh) makeresident ret==STATUS_PENDING(259) AND fence_target > fence-before AND the fence ADVANCES 15// to it (poll the kernel fence page) = GPU completed the residency; 16// C) alloc #2 (distinct, fresh) makeresident ret==259 AND fence_target2 > fence_target1 AND completes 17// (per-allocation residency, real async work each time -- not a stuck constant); 18// D) TAMPER: T1 bogus paging_queue -> neg; T2 bogus allocation handle in list -> neg; T3 alloc_count=0 -> neg; 19// T4 on a non-dxg fd -> -ENOTTY. 20// Marker -> knowledge/status/gpu_dxg.log (DXGRESGATE). raw syscalls only. NO-WAVE: pins memory resident; NO compute/throughput (R7). ZERO speedup. 21// license_tier: ORIGINAL 22import "nx_syscalls.nx" 23 24const ENUM2_CODE: i64 = 0xC0104714 25const QAI_CODE: i64 = 0xC0184709 26const OAFL_CODE: i64 = 0xC00C4701 27const CDEV_CODE: i64 = 0xC0404702 28const CPQ_CODE: i64 = 0xC0204707 29const CALLOC_CODE: i64 = 0xC0484706 30const MKRES_CODE: i64 = 0xC030470B 31const STATUS_PENDING: i64 = 259 32 33func p(s: *u8) -> i64 { var nn: i64=0; while s[nn]!=(0 as u8){nn=nn+1} sys_write(1,s,nn); return 0 } 34func fp(fd: i64, s: *u8) -> i64 { var nn: i64=0; while s[nn]!=(0 as u8){nn=nn+1} sys_write(fd,s,nn); return 0 } 35func n(v: i64) -> i64 { let bb: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m;sys_write(1,"-" as *u8,1)}; let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48;k=1}; while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1}; var i: i64=0; while i<k{bb[i]=t[k-1-i];i=i+1}; sys_write(1,bb,k); return 0 } 36func x(v: i64) -> i64 { p("0x" as *u8); let bb:*u8=sys_mmap(20); var k:i64=0; var m:i64=v; if m==0{bb[0]=48;k=1}; while m>0{ let d:i64=m&15; if d<10{bb[k]=(48+d) as u8}else{bb[k]=(87+d) as u8}; m=(m>>4); k=k+1 } var i:i64=0; let o:*u8=sys_mmap(20); while i<k{o[i]=bb[k-1-i];i=i+1} sys_write(1,o,k); return 0 } 37func fx(fd: i64, v: i64) -> i64 { let bb:*u8=sys_mmap(20); var k:i64=0; var m:i64=v; if m==0{bb[0]=48;k=1}; while m>0{ let d:i64=m&15; if d<10{bb[k]=(48+d) as u8}else{bb[k]=(87+d) as u8}; m=(m>>4); k=k+1 } let o:*u8=sys_mmap(20); var i:i64=0; while i<k{o[i]=bb[k-1-i];i=i+1} fp(fd,"0x" as *u8); sys_write(fd,o,k); return 0 } 38func fn(fd: i64, v: i64) -> i64 { let bb: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m;fp(fd,"-" as *u8)}; let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48;k=1}; while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1}; var i: i64=0; while i<k{bb[i]=t[k-1-i];i=i+1}; sys_write(fd,bb,k); return 0 } 39func rd32(buf: *u8, off: i64) -> i64 { return (buf[off] as i64)|((buf[off+1] as i64)<<8)|((buf[off+2] as i64)<<16)|((buf[off+3] as i64)<<24) } 40func rd64(buf: *u8, off: i64) -> i64 { let q: *i64 = (buf as i64 + off) as *i64; return q[0] } 41func setu32(buf: *u8, off: i64, val: i64) -> i64 { let w: *u8 = (buf as i64 + off) as *u8; w[0]=(val&0xff) as u8; w[1]=((val>>8)&0xff) as u8; w[2]=((val>>16)&0xff) as u8; w[3]=((val>>24)&0xff) as u8; return 0 } 42func setu64(buf: *u8, off: i64, val: i64) -> i64 { let q: *i64 = (buf as i64 + off) as *i64; q[0]=val; return 0 } 43 44func query_type(fd: i64, handle: i64, qtype: i64, psize: i64, outv: *i64) -> i64 { 45 let priv: *u8 = sys_mmap(64); var zz: i64 = 0; while zz < 64 { priv[zz] = 0 as u8; zz = zz + 1 } 46 let req: *u8 = sys_mmap(64); var y: i64 = 0; while y < 64 { req[y] = 0 as u8; y = y + 1 } 47 let h: *i64 = (req as i64 + 0) as *i64; h[0] = (handle & 0xffffffff) | ((qtype & 0xffffffff) << 32) 48 let pd: *i64 = (req as i64 + 8) as *i64; pd[0] = priv as i64 49 let pds: *i64 = (req as i64 + 16) as *i64; pds[0] = psize & 0xffffffff 50 let ret: i64 = sys_ioctl(fd, QAI_CODE, req as i64); outv[0] = rd32(priv, 0); return ret 51} 52func open_from_luid(fd: i64, luid_lo: i64, luid_hi: i64, outh: *i64) -> i64 { 53 let req: *u8 = sys_mmap(64); var y: i64 = 0; while y < 64 { req[y] = 0 as u8; y = y + 1 } 54 let lo: *i64 = (req as i64 + 0) as *i64; lo[0] = (luid_lo & 0xffffffff) | ((luid_hi & 0xffffffff) << 32) 55 let ret: i64 = sys_ioctl(fd, OAFL_CODE, req as i64); outh[0] = rd32(req, 8); return ret 56} 57func create_device(fd: i64, adapter: i64, outd: *i64) -> i64 { 58 let buf: *u8 = sys_mmap(512); var bz: i64 = 0; while bz < 512 { buf[bz] = 0 as u8; bz = bz + 1 } 59 setu32(buf, 0, adapter & 0xffffffff) 60 let ret: i64 = sys_ioctl(fd, CDEV_CODE, buf as i64); outd[0] = rd32(buf, 12); return ret 61} 62func create_pq(fd: i64, device: i64, outpq: *i64, outfva: *i64) -> i64 { 63 let buf: *u8 = sys_mmap(512); var bz: i64 = 0; while bz < 512 { buf[bz] = 0 as u8; bz = bz + 1 } 64 setu32(buf, 0, device & 0xffffffff) 65 let ret: i64 = sys_ioctl(fd, CPQ_CODE, buf as i64); outpq[0] = rd32(buf, 8); outfva[0] = rd64(buf, 16); return ret 66} 67func alloc_eh(fd: i64, device: i64, sysmem: *u8, outh: *i64) -> i64 { 68 let desc: *u8 = sys_mmap(64); var dz: i64 = 0; while dz < 64 { desc[dz] = 0 as u8; dz = dz + 1 } 69 setu32(desc, 0, 1); setu64(desc, 8, 65536) 70 let entry: *u8 = sys_mmap(256); var ez: i64 = 0; while ez < 256 { entry[ez] = 0 as u8; ez = ez + 1 } 71 setu64(entry, 8, sysmem as i64) 72 let buf: *u8 = sys_mmap(512); var bz: i64 = 0; while bz < 512 { buf[bz] = 0 as u8; bz = bz + 1 } 73 setu32(buf, 0, device & 0xffffffff); setu64(buf, 32, desc as i64); setu32(buf, 40, 0) 74 setu32(buf, 44, 1); setu64(buf, 48, entry as i64); setu32(buf, 56, 0x10020) 75 let ret: i64 = sys_ioctl(fd, CALLOC_CODE, buf as i64); outh[0] = rd32(entry, 0); return ret 76} 77// makeresident a single allocation handle (with a 1-entry priority list). OUT fence@32->outf[0], trim@40->outt[0]. 78func makeresident(fd: i64, pq: i64, alloc_handle: i64, alloc_count: i64, flags: i64, outf: *i64, outt: *i64) -> i64 { 79 let alist: *u8 = sys_mmap(64); setu32(alist, 0, alloc_handle & 0xffffffff) 80 let plist: *u8 = sys_mmap(64); setu32(plist, 0, 0) 81 let buf: *u8 = sys_mmap(256); var bz: i64 = 0; while bz < 256 { buf[bz] = 0 as u8; bz = bz + 1 } 82 setu32(buf, 0, pq & 0xffffffff); setu32(buf, 4, alloc_count) 83 setu64(buf, 8, alist as i64); setu64(buf, 16, plist as i64); setu32(buf, 24, flags) 84 let ret: i64 = sys_ioctl(fd, MKRES_CODE, buf as i64) 85 outf[0] = rd64(buf, 32); outt[0] = rd64(buf, 40); return ret 86} 87func wait_fence(fence_va: i64, target: i64) -> i64 { 88 let fpp: *i64 = fence_va as *i64 89 var iters: i64 = 0; var reached: i64 = 0 90 while iters < 500000000 { if fpp[0] >= target { reached = 1; iters = 500000000 } else { iters = iters + 1 } } 91 return reached 92} 93 94func main() -> i64 { 95 p("=== SOVEREIGN-GPU R4f gate (raw /dev/dxg LX_DXMAKERESIDENT -> make allocations GPU-resident on the 5080) ===\n" as *u8) 96 let fd: i64 = sys_openat_rd("/dev/dxg" as *u8) 97 if fd < 0 { p("open(/dev/dxg) failed\n" as *u8); sys_exit(1); return 1 } 98 let ainfo: *u8 = sys_mmap(4096); var z: i64 = 0; while z < 4096 { ainfo[z] = 0 as u8; z = z + 1 } 99 let ereq: *u8 = sys_mmap(64); ereq[0] = 8 as u8; let r8: *i64 = (ereq as i64 + 8) as *i64; r8[0] = ainfo as i64 100 let eret: i64 = sys_ioctl(fd, ENUM2_CODE, ereq as i64); let nc: i64 = rd32(ereq, 0) 101 let v: *i64 = sys_mmap(16); var n_discrete: i64 = 0; var disc_lo: i64 = 0; var disc_hi: i64 = 0 102 var ai: i64 = 0 103 while ai < nc { 104 let base: i64 = ai * 20; let eh: i64 = rd32(ainfo, base) 105 let qret: i64 = query_type(fd, eh, 15, 4, v); let t: i64 = v[0] 106 if qret == 0 { if ((t>>4)&1) == 1 { if ((t>>2)&1) == 0 { n_discrete = n_discrete + 1; disc_lo = rd32(ainfo, base+4); disc_hi = rd32(ainfo, base+8) } } } 107 ai = ai + 1 108 } 109 let ah: *i64 = sys_mmap(16); let aor: i64 = open_from_luid(fd, disc_lo, disc_hi, ah) 110 let dh: *i64 = sys_mmap(16); let dr: i64 = create_device(fd, ah[0], dh); let device: i64 = dh[0] 111 let pqh: *i64 = sys_mmap(16); let fvah: *i64 = sys_mmap(16); let pqr: i64 = create_pq(fd, device, pqh, fvah); let pq: i64 = pqh[0]; let fence_va: i64 = fvah[0] 112 let sm1: *u8 = sys_mmap(65536); var s1: i64 = 0; while s1 < 65536 { sm1[s1] = 0 as u8; s1 = s1 + 1 } 113 let sm2: *u8 = sys_mmap(65536); var s2: i64 = 0; while s2 < 65536 { sm2[s2] = 0 as u8; s2 = s2 + 1 } 114 let a1: *i64 = sys_mmap(16); alloc_eh(fd, device, sm1, a1); let alloc1: i64 = a1[0] 115 let a2: *i64 = sys_mmap(16); alloc_eh(fd, device, sm2, a2); let alloc2: i64 = a2[0] 116 let fp0: *i64 = fence_va as *i64; let fence_before: i64 = fp0[0] 117 p(" chain: device=" as *u8); x(device); p(" pq=" as *u8); x(pq); p(" alloc1=" as *u8); x(alloc1); p(" alloc2=" as *u8); x(alloc2); p(" fence_before=" as *u8); n(fence_before); p("\n" as *u8) 118 119 let f1: *i64 = sys_mmap(16); let tr1: *i64 = sys_mmap(16) 120 let r1: i64 = makeresident(fd, pq, alloc1, 1, 0, f1, tr1); let done1: i64 = wait_fence(fence_va, f1[0]) 121 p(" MAKERESIDENT #1 ret=" as *u8); n(r1); p(" fence_target=" as *u8); n(f1[0]); p(" trim=" as *u8); n(tr1[0]); p(" fence_reached=" as *u8); n(done1); p("\n" as *u8) 122 let f2: *i64 = sys_mmap(16); let tr2: *i64 = sys_mmap(16) 123 let r2: i64 = makeresident(fd, pq, alloc2, 1, 0, f2, tr2); let done2: i64 = wait_fence(fence_va, f2[0]) 124 p(" MAKERESIDENT #2 ret=" as *u8); n(r2); p(" fence_target=" as *u8); n(f2[0]); p(" trim=" as *u8); n(tr2[0]); p(" fence_reached=" as *u8); n(done2); p("\n" as *u8) 125 126 // ---- TAMPER matrix ---- 127 let tf: *i64 = sys_mmap(16); let tt: *i64 = sys_mmap(16) 128 let t1: i64 = makeresident(fd, 0xdeadbeef, alloc1, 1, 0, tf, tt) // bogus paging queue 129 let t2: i64 = makeresident(fd, pq, 0xdeadbeef, 1, 0, tf, tt) // bogus allocation handle 130 let t3: i64 = makeresident(fd, pq, alloc1, 0, 0, tf, tt) // alloc_count = 0 131 let nfd: i64 = sys_openat_rd("/dev/null" as *u8) 132 let t4: i64 = makeresident(nfd, pq, alloc1, 1, 0, tf, tt) // non-dxg fd 133 if nfd >= 0 { sys_close(nfd) } 134 p(" [tamper] bogus-pq=" as *u8); n(t1); p(" | bogus-alloc=" as *u8); n(t2); p(" | count=0=" as *u8); n(t3); p(" | non-dxg=" as *u8); n(t4); p("\n" as *u8) 135 sys_close(fd) 136 137 var res1: i64 = 0; if r1 == STATUS_PENDING { if f1[0] > fence_before { res1 = 1 } } 138 var res2: i64 = 0; if r2 == STATUS_PENDING { if f2[0] > f1[0] { res2 = 1 } } 139 var tamper_ok: i64 = 0; if t1 < 0 { if t2 < 0 { if t3 < 0 { if t4 < 0 { tamper_ok = 1 } } } } 140 141 var pass: i64 = 0 142 if eret == 0 { if n_discrete == 1 { if aor == 0 { if dr == 0 { if pqr == 0 { 143 if res1 == 1 { if done1 == 1 { if res2 == 1 { if done2 == 1 { if tamper_ok == 1 { pass = 1 } } } } } } } } } } 144 145 p(" checks: chain_ok=" as *u8); var ch: i64=0; if eret==0 { if aor==0 { if dr==0 { if pqr==0 { ch=1 } } } } n(ch) 146 p(" res1_pending=" as *u8); n(res1); p(" fence1_done=" as *u8); n(done1); p(" res2_pending=" as *u8); n(res2); p(" fence2_done=" as *u8); n(done2); p(" tamper_ok=" as *u8); n(tamper_ok); p("\n" as *u8) 147 148 let lfd: i64 = sys_openat_append("knowledge/status/gpu_dxg.log" as *u8, 0x1a4) 149 if pass == 1 { 150 p("DXGRESGATE verdict=GREEN reason=raw-/dev/dxg-LX_DXMAKERESIDENT-pins-real-allocations-GPU-resident-on-the-5080 (STATUS_PENDING; the paging fence ADVANCES to paging_fence_value via the R4c kernel fence page = GPU completed residency; two distinct allocations -> two advancing fence targets; bogus-pq/bogus-alloc/count=0/non-dxg tampers all negative; wrapper-free) SCOPE=residency-only-NO-throughput; command-submit=R4g\n" as *u8) 151 if lfd >= 0 { 152 fp(lfd, "DXGRESGATE verdict=GREEN rung=R4f-make-resident device=discrete-RTX5080 via=raw-/dev/dxg-LX_DXMAKERESIDENT(0xC030470B,size48,fence@32) paging_queue=" as *u8); fx(lfd, pq) 153 fp(lfd, " alloc1=" as *u8); fx(lfd, alloc1); fp(lfd, " alloc2=" as *u8); fx(lfd, alloc2) 154 fp(lfd, " fence_before=" as *u8); fn(lfd, fence_before); fp(lfd, " fence_target1=" as *u8); fn(lfd, f1[0]); fp(lfd, " fence_target2=" as *u8); fn(lfd, f2[0]) 155 fp(lfd, " STATUS_PENDING=259 fence_advanced=1 tamper=rejected(bogus-pq+bogus-alloc+count0+non-dxg) wrapper-free scope=residency-only-NO-throughput next=R4g-command-buffer+LX_DXSUBMITCOMMAND\n" as *u8) 156 sys_close(lfd) 157 } 158 sys_exit(0); return 0 159 } 160 p("DXGRESGATE verdict=RED (one of chain/res1/fence1/res2/fence2/tamper not satisfied)\n" as *u8) 161 if lfd >= 0 { fp(lfd, "DXGRESGATE verdict=RED see-console\n" as *u8); sys_close(lfd) } 162 sys_exit(1) 163 return 1 164}