nx_alu_op_kind.nx source

1// nx_alu_op_kind.nx -- SINGLE SOURCE of the ALU op -> .nxgate cell-kind map. 2// 3// SIL-3 closure (the Verifier organ's load-bearing seam). The divergence- 4// causing decision -- which gate kind each RV64IM ALU op lowers to, INCLUDING 5// the DIV/REM-as-ADD seed stub -- lives HERE, in one place, so that BOTH: 6// (a) the shipping text emitter synth_emit_alu_gates.nx, and 7// (b) the in-memory netlist the gate-sim verifies nx_alu_netlist_build.nx 8// derive from it. ONE SOURCE => nx_gsim_run provably verifies the emitter's 9// ACTUAL op->kind decisions, not a hand-kept copy (the old two-sources gap that 10// nx_alu_netlist_test.nx had to re-encode by hand). 11// 12// V1: every op lowers to ONE combinational cell (the seed emitter's shape). 13// When a real divider sub-network lands (nx_alu_divider*.nx, already proven), 14// this generalises to a sub-network emitter and the SAME verifier flips DIV 15// from DIVERGE to MATCH -- the invention loop's first hardware capability. 16// 17// Returns 0 - 1 for INVALID / out-of-range (caller emits nothing). 18 19import "nishi_synth_gates.nx" 20import "rv64im_min_alu.nx" 21 22func nx_alu_op_to_gate_kind(op: i64) -> i64 { 23 if op == NX_RV64IM_ALU_ADD { return NX_GATE_KIND_ADD } 24 if op == NX_RV64IM_ALU_SUB { return NX_GATE_KIND_SUB } 25 if op == NX_RV64IM_ALU_AND { return NX_GATE_KIND_AND } 26 if op == NX_RV64IM_ALU_OR { return NX_GATE_KIND_OR } 27 if op == NX_RV64IM_ALU_XOR { return NX_GATE_KIND_XOR } 28 if op == NX_RV64IM_ALU_SLL { return NX_GATE_KIND_SHL } 29 if op == NX_RV64IM_ALU_SRL { return NX_GATE_KIND_SHR } 30 if op == NX_RV64IM_ALU_SRA { return NX_GATE_KIND_SAR } 31 if op == NX_RV64IM_ALU_SLT { return NX_GATE_KIND_LT } 32 if op == NX_RV64IM_ALU_SLTU { return NX_GATE_KIND_LTU } 33 if op == NX_RV64IM_ALU_MUL { return NX_GATE_KIND_MUL } 34 // W-suffix: seed emits the base op (sign-extension cells are TODO_SILICON). 35 if op == NX_RV64IM_ALU_ADDW { return NX_GATE_KIND_ADD } 36 if op == NX_RV64IM_ALU_SUBW { return NX_GATE_KIND_SUB } 37 if op == NX_RV64IM_ALU_SLLW { return NX_GATE_KIND_SHL } 38 if op == NX_RV64IM_ALU_SRLW { return NX_GATE_KIND_SHR } 39 if op == NX_RV64IM_ALU_SRAW { return NX_GATE_KIND_SAR } 40 // mulh family: seed emits low-product MUL (high-product tree is TODO_SILICON). 41 if op == NX_RV64IM_ALU_MULH { return NX_GATE_KIND_MUL } 42 if op == NX_RV64IM_ALU_MULHSU { return NX_GATE_KIND_MUL } 43 if op == NX_RV64IM_ALU_MULHU { return NX_GATE_KIND_MUL } 44 if op == NX_RV64IM_ALU_MULW { return NX_GATE_KIND_MUL } 45 // div/rem family: the SIL-1 stub -- ADD instead of a divider FSM. 46 if op == NX_RV64IM_ALU_DIV { return NX_GATE_KIND_ADD } // TODO_SILICON proper divider 47 if op == NX_RV64IM_ALU_DIVU { return NX_GATE_KIND_ADD } 48 if op == NX_RV64IM_ALU_REM { return NX_GATE_KIND_ADD } 49 if op == NX_RV64IM_ALU_REMU { return NX_GATE_KIND_ADD } 50 if op == NX_RV64IM_ALU_DIVW { return NX_GATE_KIND_ADD } 51 if op == NX_RV64IM_ALU_DIVUW { return NX_GATE_KIND_ADD } 52 if op == NX_RV64IM_ALU_REMW { return NX_GATE_KIND_ADD } 53 if op == NX_RV64IM_ALU_REMUW { return NX_GATE_KIND_ADD } 54 return 0 - 1 55}