nx_alu_op_kind.nx

nx_alu_op_kind.nx -- SINGLE SOURCE of the ALU op -> .nxgate cell-kind map. SIL-3 closure (the Verifier organ's load-bearing seam). The divergence- causing decision -- which gate kind each RV64IM ALU op lowers to, INCLUDING the DIV/REM-as-ADD seed stub -- lives HERE, in one place, so that BOTH: (a) the shipping text emitter synth_emit_alu_gates.nx, and (b) the in-memory netlist the gate-sim verifies nx_alu_netlist_build.nx derive from it. ONE SOURCE => nx_gsim_run provably verifies the emitter's ACTUAL op->kind decisions, not a hand-kept copy (the old two-sources gap that nx_alu_netlist_test.nx had to re-encode by hand). V1: every op lowers to ONE combinational cell (the seed emitter's shape). When a real divider sub-network lands (nx_alu_divider*.nx, already proven), this generalises to a sub-network emitter and the SAME verifier flips DIV from DIVERGE to MATCH -- the invention loop's first hardware capability. Returns 0 - 1 for INVALID / out-of-range (caller emits nothing).