code wiki / alu
topic: alu
20 modules sharing the alu name family (derived from the tree's prefix discipline).
| module | description | lines | funcs |
|---|---|---|---|
| nx_alu_divider.nx | SYNTHESIZE a correct divider as a gate-network (the | 109 | 5 |
| nx_alu_divider_alu_test.nx | HARDWARE INVENTIONS verified IN the ALU. Builds | 199 | 4 |
| nx_alu_divider_exhaustive_test.nx | the divider EXCEED on the VERIFICATION | 67 | 3 |
| nx_alu_divider_floor_test.nx | COMPLETE THE FLOOR (honest step 0 toward the | 87 | 3 |
| nx_alu_divider_newton.nx | MULTIPLICATIVE (Newton-Raphson reciprocal) divider: | 160 | 6 |
| nx_alu_divider_proof_test.nx | the divider's PROOF step (theory -> PROOF -> | 80 | 3 |
| nx_alu_divider_r4.nx | the divider's QUANTITATIVE exceed: a RADIX-4 divider | 65 | 1 |
| nx_alu_divider_r4_test.nx | the divider's FULL qual+quant exceed proof. | 75 | 4 |
| nx_alu_divider_r8.nx | radix-8 divider (3 quotient bits/iteration => W/3 | 54 | 1 |
| nx_alu_divider_race_test.nx | the RACE step (theory -> proof -> RACED). Not a | 82 | 6 |
| nx_alu_divider_test.nx | proves the SYNTHESIZED divider gate-network computes | 55 | 4 |
| nx_alu_emit_text_test.nx | SOVEREIGN gate (NishiLang verdict, no shell/grep): | 96 | 4 |
| nx_alu_from_gates_test.nx | the team builds ARITHMETIC from BITS UP. The same gate-level | 84 | 7 |
| nx_alu_netlist_build.nx | builds the ALU op-select netlist IN MEMORY as the | 102 | 2 |
| nx_alu_netlist_build_div.nx | the ALU op-select netlist with the PROVEN | 175 | 5 |
| nx_alu_netlist_full_test.nx | SIL-3 VERIFIER over the FULL 29-op ALU. | 99 | 3 |
| nx_alu_netlist_test.nx | VERIFIER on the REAL ALU op-select topology | 86 | 4 |
| nx_alu_op_kind.nx | SINGLE SOURCE of the ALU op -> .nxgate cell-kind map. | 55 | 1 |
| nx_alu_select.nx | THE one ALU op-select builder, written against NxCellSink. | 163 | 5 |
| nx_alu_select_mem_test.nx | proves the ONE unified builder (nx_alu_build_select) | 74 | 4 |