code wiki / _hdl_build / nx_alu_divider_test.nx

nx_alu_divider_test.nx

buildroot/runtime/_hdl_build/nx_alu_divider_test.nx

2312 B55 linesdepth 8pulls 8 transitivereach 0 importersview sourcekind gate/prooftopic alu
docsdependenciesstructsconstsfunctions

about

nx_alu_divider_test.nx -- proves the SYNTHESIZED divider gate-network computes division 1:1 vs behavioral a/b + a%b (the invention engine's first hardware invention; replaces the SIL-1 DIV-as-ADD stub with a VERIFIED-correct network). Synthesizes an 8-stage restoring divider, then sims it over 4 vectors and asserts quotient == a/b AND remainder == a%b for each. Known answer (FAIL LOUD): "28 4 11 1 17 0 7 2 " = q,r for 200/7, 100/9, 255/15, 37/5.

dependencies 1 imports · 0 importers

nx_alu_divider.nx nx_alu_divider_test.nx

imports: nx_alu_divider.nx

imported by: nobody (leaf or entry point)

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

main nx_div_synth nx_sink_init_mem nx_div_synth_sink nx_sink_const nx_hdl_wire nx_hdl_signal_alloc nx_hdl_kind_is_valid nx_hdl_width_is_valid nx_sink_cell nx_hdl_wire ↻ sys_mmap _check nx_gsim_run nx_gsim_kind_supported nx_gsim_eval_cell _emit_num _nl

structs

none

consts

none

functions

11func _emit_num(v: i64) -> i64
called by 1: _check
19func _nl() -> i64 { let z: *u8 = sys_mmap(2); z[0] = 10; sys_write(1, z, 1); return 0 }
called by 1: main
23func _check(g: *NxGsim, quo_net: i64, rem_net: i64, a: i64, b: i64) -> i64
called by 1: main calls 2: nx_gsim_run_emit_num
35func main() -> i64
calls 3: nx_div_synth_check_nl