nx_nxgate_sim.nx

nx_nxgate_sim.nx -- gate-level FUNCTIONAL simulator: the VERIFIER organ's hardware oracle (closes SIL-3, "no gate-level functional verification"). The .nxgate netlist (nishi_synth_gates.nx) is word-level cells: each cell is a kind (ADD/SUB/MUX/EQ/AND/...) with a fanout net + fanin nets. This module evaluates such a netlist over input vectors so we can assert it computes 1:1 what the behavioral RTL (rv64im_min_alu.nx) computes. WHY this matters: the ALU gate emitter currently emits an ADD cell for DIV/REM (the SIL-1 stub), so a faithful functional sim will DIVERGE from behavioral DIV -- i.e. it CATCHES the silent gate-emit miscompile that today's structural-only smokes miss. V1: combinational, word-level, 64-bit (i64) values; cells assumed in topological order (the synth emitter builds sub-results before consumers). LOUD on any unsupported/sequential kind -- never silently miscomputes (Cardinal: build intelligence, fail loud). Reuses the real NX_GATE_KIND_* enum from nishi_synth_gates.nx (single source of truth -- DRY). 5W1H feedback hook: nx_gsim_diff returns the mismatch count; a future variant records WHICH vector + WHICH net diverged + the expected-vs-got, the actionable diagnostic the invention loop's Generator consumes.