nishi_synth_gates.nx

nishi_synth_gates.nx -- sovereign gate-netlist emitter. Replaces Verilog as the canonical synth output target. Emits a NishiLang-native gate-netlist text format (.nxgate) that downstream nishi-pnr can consume. No Verilog syntax anywhere -- no `module`, no `wire`, no `assign`, no `always_comb`, no `endmodule`. Per the operator's cardinal (2026-05-26): "our own verilog without any of this being something we can be legally hit on" + the [[feedback-open-source-licensed-is-still-third-party]] memory: Verilog 2005 (IEEE 1364) is an external spec; emitting it bakes in a third-party dependency even though the emitter itself is ours. The .nxgate format below is fully sovereign -- the SPEC is here, the EMITTER is here, the CONSUMER (nishi-pnr, future) is also here. The Verilog emitter (nishi_synth.nx + synth_emit_alu.nx) stays as a Wheeler-only test comparator per [[feedback-c-is-wheeler-test-only]] -- run both emitters in parallel during development, diff the resulting netlists for correctness, NEVER ship the Verilog path as canonical. .nxgate v1 format spec: .NXGATE 1 format version .MODULE <name> one per file .PORT IN <name> width=<W> input port; W in 1..512 .PORT OUT <name> width=<W> output port .PORT INOUT <name> width=<W> bidirectional port .PORT CLK <name> clock (always 1-bit) .PORT RST <name> reset (always 1-bit) .NET <id> width=<W> internal net; id 0..n_nets-1 .CELL <id> kind=<K> fanout=<net> combinational cell fanin=<net>,<net>,... .FLOP <id> kind=DFF fanout=<net> sequential cell (D-flipflop) d=<net> clk=<port> rst=<port> .CONST <id> width=<W> value=<V> compile-time constant .END module end Cell kinds (sealed):