nishi_synth.nx

nishi_synth.nx -- WHEELER-ONLY Verilog emitter. !!! STATUS 2026-05-26: DEPRECATED FROM THE CANONICAL EMIT PATH. !!! This file emits Verilog 2005. Per the operator's cardinal of 2026-05-26 ("our own verilog without any of this being something we can be legally hit on") + [[feedback-open-source-licensed- is-still-third-party]] + the audit in hdl/SILICON_SOVEREIGNTY_AUDIT.md, Verilog is an EXTERNAL spec (IEEE 1364) and emitting it bakes in third-party tools as essential to the path. The sovereign canonical emit path is hdl/nishi_synth_gates.nx (.nxgate v1 format, ours). This file STAYS for Wheeler-only test purposes per [[feedback-c-is-wheeler-test-only]]: - During development, run BOTH emitters in parallel - Diff the resulting netlists for correctness - NEVER ship Verilog as the canonical artifact All consumers of THIS file must be Wheeler test harnesses, not production paths. If you find a non-Wheeler caller, file it as a sovereignty regression. Reads an NxHdlModule (declared via nishi_hdl_primitives.nx constructors) and emits a Verilog 2005 module definition. Status: SEED. 2026-05-26. Module-shape emit only -- declares ports, wires, regs. The combinational LOGIC that drives the outputs (decoder lookup tables, ALU compute, CSR mux, etc.) is emitted by per-module "logic emitter" functions that follow-on commits will write -- one per RTL module under hdl/. This is the structural skeleton; the behavioural layer plugs in behind a small extension point (nx_synth_emit_logic_<module>).