synth_emit_alu.nx

synth_emit_alu.nx -- per-module Verilog logic emitter for the ALU. First per-RTL-module logic emitter -- demonstrates the pattern the remaining 5 (decoder, regfile, csr, clint, uart) will follow. Reads the declared NxRv64imAluPorts handles (op_in, a_in, b_in, result) + emits a combinational `always_comb` block with a case statement over the 29 NX_RV64IM_ALU_* op codes. Plugged into the nishi_synth skeleton between the BEGIN/END logic-injection markers. Status: SEED. 2026-05-26. Pattern reference for the remaining 5 module emitters per hdl/HACKING.md "Adding a per-module logic emitter" recipe.