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rv64im_min_alu.nx

buildroot/runtime/_hdl_build/rv64im_min_alu.nx

13845 B355 linesdepth 3pulls 3 transitivereach 85 importersview sourcekind librarytopic rv64im

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about

rv64im_min_alu.nx -- RV64IM-min ALU. Combinational 64-bit ALU covering every operation the decoder (rv64im_min_decoder.nx) can dispatch to: - RV64I base: add/sub/sll/slt/sltu/xor/srl/sra/or/and - RV64I-64: addw/subw/sllw/srlw/sraw (32-bit ops with sign-ext) - M extension: mul/mulh/mulhsu/mulhu/div/divu/rem/remu (64-bit) - M ext-32: mulw/divw/divuw/remw/remuw (32-bit with sign-ext) Each operation gets a sealed-enum op code; the executor (future commit) routes the decoded NX_RV64IM_OP_* + funct3 + funct7 through nx_rv64im_alu_select() to derive the ALU op code, then drives nx_rv64im_alu_compute() with the operand bits. Status: SEED. 2026-05-26. Pure-function compute layer; the HDL-graph builder declares the module shape so nishi-sim / nishi-synth can drive it later.

dependencies 2 imports · 73 importers

diagram shows first 10 each side; +0 more imports, +63 more importers in the complete lists below.

imports: nx_syscalls.nxnishi_hdl_primitives.nx

imported by: nx_alu_divider_alu_test.nxnx_alu_netlist_build.nxnx_alu_netlist_build_div.nxnx_alu_netlist_full_test.nxnx_alu_op_kind.nxnx_alu_select.nxnx_alu_select_mem_test.nxnx_cpu_rtype_exec_test.nxnx_emu_bench.nxnx_evo_isa_sov.nxnx_fpga_alu_gate.nxnx_fpga_alu_verilog_gate.nxnx_fpga_boot_gate.nxnx_fpga_cmp_gate.nxnx_fpga_cpu2_gate.nxnx_fpga_cpu3_gate.nxnx_fpga_cpu4_gate.nxnx_fpga_cpu5_gate.nxnx_fpga_cpu6_gate.nxnx_fpga_cpu7_gate.nxnx_fpga_cpu8_gate.nxnx_fpga_cpu9_gate.nxnx_fpga_cpu_gate.nxnx_fpga_div_gate.nxnx_fpga_ecall_gate.nxnx_fpga_lui_gate.nxnx_fpga_mul_gate.nxnx_fpga_rexec_gate.nxnx_fpga_rtype_gate.nxnx_fpga_sdiv_gate.nxnx_fpga_shift_gate.nxnx_geneal_energy_sov.nxnx_isa_cf_sov.nxnx_isa_equiv_sov.nxnx_isa_loop_sov.nxnx_isa_run_sov.nxnx_isa_synth_sov.nxnx_mulh_diag.nxnx_nhdl_gate.nxnx_nhdl_scorecard_gate.nxnx_nxc_baremetal.nxnx_nxc_run.nxnx_recip64_scalar_test.nxnx_recip64_test.nxnx_rtype_control.nxnx_rv64_amo_gate.nxnx_rv64_csr_trap_oracle.nxnx_rv64_fast_dev_gate.nxnx_rv64_fast_gate.nxnx_rv64_kernel_gate.nxnx_rv64_mmu_oracle.nxnx_rv64_qemu_fuzz.nxnx_rv64_qemu_oracle.nxnx_rv64_realc_gate.nxnx_rv64_run_bin.nxnx_rv64_sdeleg_oracle.nxnx_rv64_snapshot_gate.nxnx_rv64_timer_oracle.nxnx_rv64im_alu_proof.nxnx_rv64im_cpu_crosscheck.nxnx_simtcore.nxnx_simtcore_gate.nxrv64im_min_alu_proof.nxrv64im_min_cpu_crosscheck.nxrv64im_min_elf_loader.nxrv64im_min_gfx_gate.nxrv64im_min_hot_report.nxrv64im_min_kernel_boot_smoke.nxrv64im_min_sim.nxrv64im_min_sim_smoke.nxsynth_emit_alu.nxsynth_emit_alu_gates.nxsynth_emit_alu_gates_smoke.nx

structs

330	struct NxRv64imAluPorts

consts

28	const NX_RV64IM_ALU_INVALID: i64 = 0
31	const NX_RV64IM_ALU_ADD: i64 = 1
32	const NX_RV64IM_ALU_SUB: i64 = 2
33	const NX_RV64IM_ALU_SLL: i64 = 3 // shift left logical (low 6 bits of rs2)
34	const NX_RV64IM_ALU_SLT: i64 = 4 // set if less than (signed)
35	const NX_RV64IM_ALU_SLTU: i64 = 5 // set if less than (unsigned)
36	const NX_RV64IM_ALU_XOR: i64 = 6
37	const NX_RV64IM_ALU_SRL: i64 = 7 // shift right logical
38	const NX_RV64IM_ALU_SRA: i64 = 8 // shift right arithmetic
39	const NX_RV64IM_ALU_OR: i64 = 9
40	const NX_RV64IM_ALU_AND: i64 = 10
43	const NX_RV64IM_ALU_ADDW: i64 = 11
44	const NX_RV64IM_ALU_SUBW: i64 = 12
45	const NX_RV64IM_ALU_SLLW: i64 = 13 // shift count from low 5 bits of rs2
46	const NX_RV64IM_ALU_SRLW: i64 = 14
47	const NX_RV64IM_ALU_SRAW: i64 = 15
50	const NX_RV64IM_ALU_MUL: i64 = 16 // low 64 bits of signed*signed
51	const NX_RV64IM_ALU_MULH: i64 = 17 // high 64 bits of signed*signed
52	const NX_RV64IM_ALU_MULHSU: i64 = 18 // high 64 bits of signed*unsigned
53	const NX_RV64IM_ALU_MULHU: i64 = 19 // high 64 bits of unsigned*unsigned
54	const NX_RV64IM_ALU_DIV: i64 = 20 // signed quotient (round toward 0)
55	const NX_RV64IM_ALU_DIVU: i64 = 21
56	const NX_RV64IM_ALU_REM: i64 = 22 // signed remainder
57	const NX_RV64IM_ALU_REMU: i64 = 23
60	const NX_RV64IM_ALU_MULW: i64 = 24
61	const NX_RV64IM_ALU_DIVW: i64 = 25
62	const NX_RV64IM_ALU_DIVUW: i64 = 26
63	const NX_RV64IM_ALU_REMW: i64 = 27
64	const NX_RV64IM_ALU_REMUW: i64 = 28
66	const NX_RV64IM_ALU_N: i64 = 29
203	const NX_RV64IM_INT_MIN: i64 = 0 - 9223372036854775808 // 0x8000000000000000
204	const NX_RV64IM_ALL_ONES: i64 = 0 - 1 // 0xFFFFFFFFFFFFFFFF
327	const NX_RV64IM_ALU_WIDTH_OP: i64 = 8 // sealed enum fits 29 values
328	const NX_RV64IM_ALU_WIDTH_OPERAND: i64 = 64

functions

68	func nx_rv64im_alu_op_is_valid(op: i64) -> i64
79	func nx_rv64im_sext32(v: i64) -> i64 called by 3: nx_simt_exec_warp nx_rv64im_alu_compute nx_rv64im_sim_step
93	func nx_rv64im_ltu(a: i64, b: i64) -> i64 called by 7: main main nr64_div nx_simt_exec_warp nx_rv64im_udiv nx_rv64im_alu_compute+1
107	func nx_rv64im_lshr(a: i64, n: i64) -> i64 called by 6: nr64_msb nr64_div main main nx_rv64im_mulh_unsigned nx_rv64im_alu_compute
127	func nx_rv64im_udiv(a: i64, b: i64) -> i64 called by 4: main r64t_chk nx_rv64im_urem nx_rv64im_alu_compute calls 1: nx_rv64im_ltu
148	func nx_rv64im_urem(a: i64, b: i64) -> i64 called by 2: r64t_chk nx_rv64im_alu_compute calls 1: nx_rv64im_udiv
165	func nx_rv64im_mulh_unsigned(a: i64, b: i64) -> i64 called by 4: nr64_div nx_rv64im_mulh_signed nx_rv64im_mulh_signed_unsigned nx_rv64im_alu_compute calls 1: nx_rv64im_lshr
181	func nx_rv64im_mulh_signed(a: i64, b: i64) -> i64 called by 1: nx_rv64im_alu_compute calls 1: nx_rv64im_mulh_unsigned
190	func nx_rv64im_mulh_signed_unsigned(a: i64, b: i64) -> i64 called by 1: nx_rv64im_alu_compute calls 1: nx_rv64im_mulh_unsigned
214	func nx_rv64im_alu_compute(op: i64, a: i64, b: i64) -> i64 called by 31: _div_check main main _run_census main main+25 calls 8: nx_rv64im_lshr nx_rv64im_ltu nx_rv64im_sext32 nx_rv64im_mulh_signed nx_rv64im_mulh_signed_unsigned nx_rv64im_mulh_unsigned+2
337	func nx_rv64im_alu_build(m: NxHdlModule, ports: NxRv64imAluPorts) -> i64 called by 2: main main calls 2: nx_hdl_input nx_hdl_output