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nx_rv64_qemu_oracle.nx

buildroot/runtime/_hdl_build/nx_rv64_qemu_oracle.nx

5763 B79 linesdepth 5pulls 19 transitivereach 0 importersview sourcekind tooltopic rv64
docsdependenciesstructsconstsfunctions

about

nx_rv64_qemu_oracle.nx -- EXTERNAL-ORACLE EXECUTION VALIDATION: assemble an M-extension test program with the sovereign assembler, run it on the golden behavioral sim (rv64im_min_sim, models the UART), emit the UART bytes it produced as hex, and WRITE THE FLAT BINARY to disk so the SAME bytes can be run in real qemu-system-riscv64. If the UART output matches QEMU's, my emulator's EXECUTION semantics (esp. the tricky M-ext edge cases: high-mul, signed div rounding, unsigned div) are validated against the world's REFERENCE RISC-V implementation -- not just against my own other engines (which could share a misconception). The program emits low bytes of: sum(i^2,1..10)=385(0x81), 385/7=55(0x37), 385%7=0(0x00), mulhu(-1,-1)=..fe(0xFE), (-20)/3=-6(0xFA), (2^64-1)/2(0xFF), sentinel '*'(0x2A). expect UART = 81 37 00 fe fa ff 2a. expect_exit: 0

dependencies 13 imports · 0 importers

nx_syscalls.nx nx_itoa_lib.nx nishi_hdl_primitives.nx rv64im_min_decoder.nx rv64im_min_alu.nx rv64im_min_regfile.nx rv64im_min_csr.nx rv64im_min_clint.nx rv64im_min_uart.nx rv64im_min_virtio.nx nx_rv64_qemu_oracle.nx

diagram shows first 10 each side; +3 more imports, +0 more importers in the complete lists below.

imports: nx_syscalls.nxnx_itoa_lib.nxnishi_hdl_primitives.nxrv64im_min_decoder.nxrv64im_min_alu.nxrv64im_min_regfile.nxrv64im_min_csr.nxrv64im_min_clint.nxrv64im_min_uart.nxrv64im_min_virtio.nxrv64im_min_sim.nxnx_rv64_asm.nxnx_rv64_fast.nx

imported by: nobody (leaf or entry point)

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

main g_puts sys_write sys_mmap rvasm_assemble_str rvasm_assemble sys_mmap ↻ ra_isws ra_encode sys_mmap ↻ ra_afterword ra_isws ↻ ra_word_is ra_isws ↻ ra_reg ra_skipsep ra_isws ↻ ra_num ra_isdig ra_imm ra_skipsep ↻ ra_ishex ra_isdig ↻ ra_hexval ra_isdig ↻ ra_u ra_imm12 ra_i ra_sh6 ra_r ra_past ra_s ra_label_target ra_skipsep ↻ ra_afterword ↻ ra_find_label ra_b ra_j ra_put sys_exit

structs

none

consts

32const DMEM_BASE: i64 = 0x80000000
33const DMEM_SIZE: i64 = 65536

functions

23func g_puts(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 }
called by 2: ckmain calls 1: sys_write
28func g_pn(v: i64) -> i64 { nxi_out(v); return 0 }
called by 1: main calls 1: nxi_out
29func g_hx(v: i64) -> i64 { let b: *u8=sys_mmap(4); let n0: i64=(v>>4)&15; let n1: i64=v&15; if n0<10 { b[0]=(48+n0) as u8 } else { b[0]=(87+n0) as u8 } if n1<10 { b[1]=(48+n1) as u8 } else { b[1]=(87+n1) as u8 } b[2]=32 as u8; sys_write(1,b,3); return 0 }
called by 1: main calls 2: sys_mmapsys_write
30func ck(name: *u8, c: i64) -> i64 { if c==1 { g_puts(" PASS " as *u8) } else { g_puts(" FAIL " as *u8) } g_puts(name); g_puts("\n" as *u8); return c }
called by 1: main calls 1: g_puts
35func main() -> i64