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rv64im_min_csr.nx

buildroot/runtime/_hdl_build/rv64im_min_csr.nx

11306 B270 linesdepth 3pulls 3 transitivereach 45 importersview sourcekind librarytopic rv64im
docsdependenciesstructsconstsfunctions

about

rv64im_min_csr.nx -- RV64IM-min CSR file (M-mode only). Implements the 7 MUST CSRs from hdl/rv64im_min_target_spec.md, plus the 2 SHOULD CSRs that the kernel reads on the bench/diag path. This is the smallest CSR set that lets the shipped nishi-os kernel boot, take a timer interrupt, and return via mret. MUST (boot fails without): mhartid (0xF14) read hart ID -- non-zero harts park at boot mscratch (0x340) 64-bit RW; trap-frame pointer swap mtvec (0x305) trap vector base (direct mode; low bits = 00) mepc (0x341) exception PC saved/restored every trap mstatus (0x300) bits 3 (MIE), 7 (MPIE), 11-12 (MPP) mie (0x304) bit 7 (MTIE) for timer enable mcause (0x342) bit 63 = int/exc; low 8 bits = code SHOULD (kernel degrades cleanly without): mcycle (0xB00) 64-bit cycle counter; bench-only mtval (0x343) exception value; panic diagnostics only Status: SEED. 2026-05-26. Storage + access semantics + sealed- enum address dispatch. Updates are sequential (commit on clock edge); reads are combinational so back-to-back csrr/csrw works.

dependencies 2 imports · 35 importers

nx_syscalls.nx nishi_hdl_primitives.nx rv64im_min_csr.nx _gpu_run.nx _nvme_diag.nx nx_bootcap.nx nx_emu_bench.nx nx_evo_isa_sov.nx nx_geneal_energy_sov.nx nx_isa_cf_sov.nx nx_isa_equiv_sov.nx nx_isa_loop_sov.nx nx_isa_run_sov.nx

diagram shows first 10 each side; +0 more imports, +25 more importers in the complete lists below.

imports: nx_syscalls.nxnishi_hdl_primitives.nx

imported by: _gpu_run.nx_nvme_diag.nxnx_bootcap.nxnx_emu_bench.nxnx_evo_isa_sov.nxnx_geneal_energy_sov.nxnx_isa_cf_sov.nxnx_isa_equiv_sov.nxnx_isa_loop_sov.nxnx_isa_run_sov.nxnx_isa_synth_sov.nxnx_nishios_window.nxnx_nxc_baremetal.nxnx_nxc_run.nxnx_rv64_amo_gate.nxnx_rv64_csr_trap_oracle.nxnx_rv64_fast_dev_gate.nxnx_rv64_fast_gate.nxnx_rv64_kernel_gate.nxnx_rv64_mmu_oracle.nxnx_rv64_qemu_fuzz.nxnx_rv64_qemu_oracle.nxnx_rv64_realc_gate.nxnx_rv64_run_bin.nxnx_rv64_sdeleg_oracle.nxnx_rv64_snapshot_gate.nxnx_rv64_timer_oracle.nxnx_rv64im_cpu_crosscheck.nxrv64im_min_cpu_crosscheck.nxrv64im_min_elf_loader.nxrv64im_min_gfx_gate.nxrv64im_min_hot_report.nxrv64im_min_kernel_boot_smoke.nxrv64im_min_sim.nxrv64im_min_sim_smoke.nx

structs

131struct NxRv64imCsrFile
223struct NxRv64imCsrFilePorts

consts

29const NX_CSR_MSTATUS: i64 = 0x300
30const NX_CSR_MIE: i64 = 0x304
31const NX_CSR_MTVEC: i64 = 0x305
32const NX_CSR_MSCRATCH: i64 = 0x340
33const NX_CSR_MEPC: i64 = 0x341
34const NX_CSR_MCAUSE: i64 = 0x342
35const NX_CSR_MTVAL: i64 = 0x343
36const NX_CSR_MHARTID: i64 = 0xF14
37const NX_CSR_MCYCLE: i64 = 0xB00
38const NX_CSR_SATP: i64 = 0x180 // supervisor address-translation + protection (Sv39 paging)
39const NX_CSR_STVEC: i64 = 0x105 // S-mode trap vector (the kernel's own trap entry)
40const NX_CSR_SEPC: i64 = 0x141 // S-mode exception PC
41const NX_CSR_SCAUSE: i64 = 0x142 // S-mode trap cause
42const NX_CSR_MEDELEG: i64 = 0x302 // machine exception delegation -> bit c set = exception c handled in S-mode
49const NX_CSR_SLOT_MSTATUS: i64 = 0
50const NX_CSR_SLOT_MIE: i64 = 1
51const NX_CSR_SLOT_MTVEC: i64 = 2
52const NX_CSR_SLOT_MSCRATCH: i64 = 3
53const NX_CSR_SLOT_MEPC: i64 = 4
54const NX_CSR_SLOT_MCAUSE: i64 = 5
55const NX_CSR_SLOT_MTVAL: i64 = 6
56const NX_CSR_SLOT_MHARTID: i64 = 7
57const NX_CSR_SLOT_MCYCLE: i64 = 8
58const NX_CSR_SLOT_SATP: i64 = 9
59const NX_CSR_SLOT_STVEC: i64 = 10
60const NX_CSR_SLOT_SEPC: i64 = 11
61const NX_CSR_SLOT_SCAUSE: i64 = 12
62const NX_CSR_SLOT_MEDELEG: i64 = 13
63const NX_CSR_SLOT_N: i64 = 14
66const NX_CSR_OK: i64 = 0
67const NX_CSR_UNIMPLEMENTED: i64 = 1 // CSR address not in MUST or SHOULD set
68const NX_CSR_READ_ONLY: i64 = 2 // write attempted to RO csr (mhartid, mcycle)
129const NX_CSR_RESET_MSTATUS: i64 = 0x1800 // MPP=11 (M-mode), MIE=0, MPIE=0
220const NX_CSR_WIDTH_ADDR: i64 = 12 // RV64 CSR address space is 12 bits
221const NX_CSR_WIDTH_VALUE: i64 = 64
234const NX_CSR_WIDTH_VERDICT: i64 = 4

functions

76func nx_csr_addr_to_slot(addr: i64) -> i64
called by 3: nx_rv64im_csr_readnx_rv64im_csr_writenx_rv64im_csr_swap
102func nx_csr_is_read_only(slot: i64) -> i64
called by 2: nx_rv64im_csr_writenx_rv64im_csr_swap
136func nx_rv64im_csr_init(csr: *NxRv64imCsrFile, storage: *i64, hartid: i64) -> i64
called by 33: mainmainbootcap_runmainmainge_run+27
161func nx_rv64im_csr_read(csr: *NxRv64imCsrFile, addr: i64) -> i64
called by 5: nx_rv64im_xlatenx_rv64im_sim_take_trapnx_rv64im_sim_mretnx_rv64im_sim_sretnx_rv64im_sim_step calls 1: nx_csr_addr_to_slot
173func nx_rv64im_csr_write(csr: *NxRv64imCsrFile, addr: i64, value: i64) -> i64
called by 4: nx_rv64im_sim_take_trapnx_rv64im_sim_mretnx_rv64im_sim_sretnx_rv64im_sim_step calls 2: nx_csr_addr_to_slotnx_csr_is_read_only
187func nx_rv64im_csr_swap(csr: *NxRv64imCsrFile, addr: i64,
called by 1: nx_rv64im_sim_step calls 2: nx_csr_addr_to_slotnx_csr_is_read_only
212func nx_rv64im_csr_tick_mcycle(csr: *NxRv64imCsrFile) -> i64
called by 1: nx_rv64im_sim_step
236func nx_rv64im_csr_build(m: *NxHdlModule, ports: *NxRv64imCsrFilePorts) -> i64
calls 4: nx_hdl_clocknx_hdl_resetnx_hdl_inputnx_hdl_output