code wiki / _hdl_build / nx_isa_cf_sov.nx

nx_isa_cf_sov.nx

buildroot/runtime/_hdl_build/nx_isa_cf_sov.nx

20800 B409 linesdepth 5pulls 17 transitivereach 0 importersview sourcekind tooltopic isa
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about

nx_isa_cf_sov.nx -- CONTROL-FLOW rung: derive programs that BRANCH, run them on god. The straight-line ladder (nx_isa_equiv_sov) exercised god's ALU only. This rung exercises its CONTROL FLOW -- the PC takes a data-dependent path through a real RV64 conditional branch. (1) the team COMPOSES a random non-trivial 2-way conditional target T: result = if cmp(a,b) then ARM_then(a,b) else ARM_else(a,b) cmp in {a<b, a>=b, a==b, a!=b} (the sim's BLT/BGE/BEQ/BNE); each ARM is a 2-op chain over {ADD,SUB,MUL} ONLY -- no SLT -- so the BRANCH is the sole source of conditionality (the program is NOT expressible straight-line over this op set), (2) the team DERIVES a program G of the same shape by GA on T's TRAIN examples (sees only points), (3) ENCODE both to real RV64 machine code (a forward BLT/BGE/BEQ/BNE + a forward JAL skipping the other arm), run BOTH on rv64im_min_sim (god) over 12 HELD-OUT inputs, verify sim(T)==sim(G). B-type / J-type encoders are derived to round-trip the decoder's imm_b / imm_j (rv64im_min_decoder.nx:145-175); branch semantics match the sim's step loop (BRANCH funct3, rv64im_min_sim.nx:913-918). Controls: FAITHFUL (hand-built max / conditional programs with known answers prove the branch encoding) + NEGATIVE (a perturbed G the differential must catch). Only FORWARD branches this rung; backward branches (loops) are the next. license_tier: ORIGINAL

dependencies 10 imports · 0 importers

nx_syscalls.nx nx_itoa_lib.nx nishi_hdl_primitives.nx rv64im_min_decoder.nx rv64im_min_alu.nx rv64im_min_regfile.nx rv64im_min_csr.nx rv64im_min_clint.nx rv64im_min_uart.nx rv64im_min_sim.nx nx_isa_cf_sov.nx

imports: nx_syscalls.nxnx_itoa_lib.nxnishi_hdl_primitives.nxrv64im_min_decoder.nxrv64im_min_alu.nxrv64im_min_regfile.nxrv64im_min_csr.nxrv64im_min_clint.nxrv64im_min_uart.nxrv64im_min_sim.nx

imported by: nobody (leaf or entry point)

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

main cf_p sys_write cf_faithful sys_mmap cf_set cf_ha cf_hb cf_run_prog sys_mmap ↻ nx_rv64im_rf_init nx_rv64im_csr_init nx_clint_init nx_uart_init nx_rv64im_sim_init cf_emit rv_w32 rv_addi rv_lui rv_branch cf_bf3 cf_emit_arm rv_w32 ↻ rv_rtype cf_f7 cf_f3 rv_jal rv_store_imm nx_rv64im_sim_run nx_rv64im_sim_step nx_clint_tick nx_clint_update_mtip nx_rv64im_csr_tick_mcycle nx_clint_mtip_get nx_rv64im_csr_read nx_csr_addr_to_slot nx_rv64im_sim_take_trap nx_rv64im_csr_read ↻ nx_rv64im_csr_write nx_rv64im_xlate

structs

none

consts

30const EVO_MAGIC_2862933555777941757: i64 = 2862933555777941757
31const EVO_MAGIC_3037000493: i64 = 3037000493
32const EVO_MAGIC_1000000000000: i64 = 1000000000000
33const EVO_MAGIC_10000000000000: i64 = 10000000000000
34const EVO_MAGIC_1000000000: i64 = 1000000000
35const EVO_MAGIC_2654435761: i64 = 2654435761
36const EVO_MAGIC_12345: i64 = 12345
38const GLEN: i64 = 13 // [cmp] [then0 op,rs1,rs2] [then1 ...] [else0 ...] [else1 ...]
39const EVO_P: i64 = 384
40const EVO_G: i64 = 1600
41const EVO_T: i64 = 5
42const NTRAIN: i64 = 8
43const NHELD: i64 = 12
45const IR_MEM_BASE: i64 = 0x80000000
46const IR_MEM_SIZE: i64 = 8192
47const IR_TX_CAP: i64 = 256
48const RES_OFF: i64 = 0x700

functions

50func cf_rand(s: *i64) -> i64 { s[0] = s[0] * EVO_MAGIC_2862933555777941757 + EVO_MAGIC_3037000493; return (s[0] >> 17) & 0x3fffffff }
51func cf_abs(x: i64) -> i64 { if x < 0 { return 0 - x } return x }
called by 1: cf_fit
54func cf_ta(i: i64) -> i64 { if i==0 {return 6} if i==1 {return 4} if i==2 {return 9} if i==3 {return 5} if i==4 {return 7} if i==5 {return 2} if i==6 {return 8} return 3 }
called by 2: cf_composecf_fit
55func cf_tb(i: i64) -> i64 { if i==0 {return 4} if i==1 {return 7} if i==2 {return 2} if i==3 {return 9} if i==4 {return 7} if i==5 {return 5} if i==6 {return 8} return 6 }
called by 2: cf_composecf_fit
56func cf_ha(i: i64) -> i64 { if i==0 {return 3} if i==1 {return 8} if i==2 {return 11} if i==3 {return 2} if i==4 {return 10} if i==5 {return 13} if i==6 {return 7} if i==7 {return 4} if i==8 {return 12} if i==9 {return 6} if i==10 {return 9} return 5 }
57func cf_hb(i: i64) -> i64 { if i==0 {return 5} if i==1 {return 2} if i==2 {return 7} if i==3 {return 11} if i==4 {return 4} if i==5 {return 13} if i==6 {return 9} if i==7 {return 4} if i==8 {return 2} if i==9 {return 13} if i==10 {return 9} return 10 }
60func cf_aluop(op: i64, x: i64, y: i64) -> i64
called by 1: cf_arm
65func cf_reg(idx: i64, a: i64, b: i64, acc: i64) -> i64
called by 1: cf_arm
72func cf_cmp(c: i64, a: i64, b: i64) -> i64
79func cf_arm(gen: *i64, base: i64, a: i64, b: i64) -> i64
91func cf_eval(gen: *i64, a: i64, b: i64) -> i64
97func rv_addi(rd: i64, rs1: i64, imm: i64) -> i64 { return ((imm & 0xFFF) << 20) | (rs1 << 15) | (rd << 7) | 0x13 }
called by 1: cf_emit
98func rv_lui(rd: i64, imm20: i64) -> i64 { return ((imm20 & 0xFFFFF) << 12) | (rd << 7) | 0x37 }
called by 1: cf_emit
99func rv_rtype(f7: i64, rs2: i64, rs1: i64, f3: i64, rd: i64) -> i64 { return (f7 << 25) | (rs2 << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x33 }
called by 1: cf_emit_arm
100func rv_store_imm(rs2: i64, rs1: i64, f3: i64, imm: i64) -> i64 { return (((imm >> 5) & 0x7f) << 25) | (rs2 << 20) | (rs1 << 15) | (f3 << 12) | ((imm & 0x1f) << 7) | 0x23 }
called by 1: cf_emit
101func rv_branch(f3: i64, rs1: i64, rs2: i64, imm: i64) -> i64
called by 1: cf_emit
108func rv_jal(rd: i64, imm: i64) -> i64
called by 1: cf_emit
116func cf_f3(op: i64) -> i64 { return 0 }
called by 1: cf_emit_arm
117func cf_f7(op: i64) -> i64 { if op == 1 { return 0x20 } if op == 2 { return 0x01 } return 0x00 }
called by 1: cf_emit_arm
119func cf_bf3(c: i64) -> i64 { if c == 0 { return 4 } if c == 1 { return 5 } if c == 2 { return 0 } return 1 }
called by 1: cf_emit
120func rv_w32(buf: *u8, off: i64, w: i64) -> i64
called by 2: cf_emit_armcf_emit
128func cf_emit_arm(mem: *u8, o: i64, gen: *i64, base: i64) -> i64
called by 1: cf_emit calls 4: rv_w32rv_rtypecf_f7cf_f3
145func cf_emit(mem: *u8, gen: *i64, a: i64, b: i64) -> i64
162func cf_read_i64(mem: *u8, off: i64) -> i64
called by 1: cf_run_prog
168func cf_run_prog(gen: *i64, a: i64, b: i64) -> i64
192func cf_randslot(idx: i64, state: *i64) -> i64
called by 2: cf_fillcf_mut calls 1: cf_rand
200func cf_fill(gen: *i64, base: i64, state: *i64) -> i64
called by 2: cf_composecf_derive calls 1: cf_randslot
207func cf_compose(state: *i64, T: *i64) -> i64
227func cf_eval_at(pop: *i64, base: i64, a: i64, b: i64) -> i64
called by 3: cf_fitcf_seedcf_negctl calls 2: cf_cmpcf_arm
231func cf_fit(pop: *i64, base: i64, T: *i64) -> i64
244func cf_tourney(fit: *i64, state: *i64) -> i64
called by 1: cf_derive calls 1: cf_rand
249func cf_mut(gen: *i64, base: i64, state: *i64) -> i64
called by 1: cf_derive calls 2: cf_randcf_randslot
254func cf_derive(T: *i64, state: *i64, G: *i64) -> i64
287func cf_p(s: *u8) -> i64 { var n: i64 = 0; while s[n] != (0 as u8) { n = n + 1 } sys_write(1, s, n); return 0 }
292func cf_pn(v: i64) -> i64 { nxi_out(v); return 0 }
297func cf_set(g: *i64, c: i64, t0: i64,t1: i64,t2: i64, t3: i64,t4: i64,t5: i64, e0: i64,e1: i64,e2: i64, e3: i64,e4: i64,e5: i64) -> i64
called by 1: cf_faithful
301func cf_faithful() -> i64
328func cf_hw_agree(A: *i64, B: *i64) -> i64
333func cf_hw_faithful(T: *i64) -> i64
339func cf_branch_taken(T: *i64) -> i64
called by 1: cf_seed calls 3: cf_cmpcf_hacf_hb
345func cf_seed(seed: i64) -> i64
370func cf_negctl(seed: i64) -> i64
392func main() -> i64