rv64im_min_regfile.nx

rv64im_min_regfile.nx -- RV64IM-min general-purpose register file. 32 entries × 64 bits. Two combinational read ports (rs1, rs2) and one sequential write port (rd on clock-edge if write_en). x0 is hardwired to 0: reads return 0 regardless of the write history; writes to x0 are silently dropped. This matches every RV64 in-order design from the SiFive E2 series through the Rocket / BOOM cores. Out-of-order designs would rename behind this surface; Tier A FPGA bring-up is single-issue in-order so the rename layer is not needed. Status: SEED. 2026-05-26. Storage + access semantics; the HDL- graph builder declares the module shape so nishi-sim / nishi-synth can map storage onto BRAM (Tier A FPGA) or SRAM cells (Tier B+).