code wiki / _hdl_build / nx_rv64_fast_dev_gate.nx

nx_rv64_fast_dev_gate.nx

buildroot/runtime/_hdl_build/nx_rv64_fast_dev_gate.nx

7893 B110 linesdepth 5pulls 18 transitivereach 0 importersview sourcekind gate/prooftopic rv64
docsdependenciesstructsconstsfunctions

about

nx_rv64_fast_dev_gate.nx -- GATE: the DEVICE-AWARE predecoded interpreter drives a REAL virtio device, matching the golden behavioral sim, and stays faster. Eats the debt that nx_rv64_fast's speedup only helped pure compute: now the same virtio identity-read+verify driver runs on BOTH the golden sim (virtio-blk attached) and the device-aware fast interpreter, both discovering DeviceID=2 from live MMIO -- equivalence + device capability -- and the fast engine is still measurably faster on a compute-heavy workload. Teeth: no device attached -> the fast engine reads 0 (no false device). expect_exit:0

dependencies 12 imports · 0 importers

nx_syscalls.nx nishi_hdl_primitives.nx rv64im_min_decoder.nx rv64im_min_alu.nx rv64im_min_regfile.nx rv64im_min_csr.nx rv64im_min_clint.nx rv64im_min_uart.nx rv64im_min_virtio.nx rv64im_min_sim.nx nx_rv64_fast_dev_gate.nx

diagram shows first 10 each side; +2 more imports, +0 more importers in the complete lists below.

imports: nx_syscalls.nxnishi_hdl_primitives.nxrv64im_min_decoder.nxrv64im_min_alu.nxrv64im_min_regfile.nxrv64im_min_csr.nxrv64im_min_clint.nxrv64im_min_uart.nxrv64im_min_virtio.nxrv64im_min_sim.nxnx_rv64_asm.nxnx_rv64_fast.nx

imported by: nobody (leaf or entry point)

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

main g_puts sys_write sys_mmap rvasm_assemble_str rvasm_assemble sys_mmap ↻ ra_isws ra_encode sys_mmap ↻ ra_afterword ra_isws ↻ ra_word_is ra_isws ↻ ra_reg ra_skipsep ra_isws ↻ ra_num ra_isdig ra_imm ra_skipsep ↻ ra_ishex ra_isdig ↻ ra_hexval ra_isdig ↻ ra_u ra_imm12 ra_i ra_sh6 ra_r ra_past ra_s ra_label_target ra_skipsep ↻ ra_afterword ↻ ra_find_label ra_b ra_j ra_put sys_exit

structs

none

consts

24const DMEM_BASE: i64 = 0x80000000
25const DMEM_SIZE: i64 = 65536
26const DSCRATCH_OFF: i64 = 0x8000

functions

20func g_puts(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 }
called by 2: ckmain calls 1: sys_write
21func g_pn(v: i64) -> i64 { let b: *u8=sys_mmap(28); var x: i64=v; if x<0{b[0]=45;sys_write(1,b,1);x=0-x} if x==0{b[0]=48;sys_write(1,b,1);return 0} var d: i64=0; var y: i64=x; while y>0{d=d+1;y=y/10} var i: i64=d-1; y=x; while i>=0{b[i]=(48+(y%10)) as u8;y=y/10;i=i-1} sys_write(1,b,d); return 0 }
called by 1: main calls 2: sys_mmapsys_write
22func ck(name: *u8, c: i64) -> i64 { if c==1 { g_puts(" PASS " as *u8) } else { g_puts(" FAIL " as *u8) } g_puts(name); g_puts("\n" as *u8); return c }
called by 1: main calls 1: g_puts
28func mk_virtio() -> *NxVirtioMmio
called by 2: run_sim_devrun_fast_dev calls 2: sys_mmapnx_virtio_init
35func run_sim_dev(code: *u8, nb: i64, steps_out: *i64, us_out: *i64) -> i64
called by 1: main calls 11: sys_mmapnx_rv64im_rf_initnx_rv64im_csr_initnx_clint_initnx_uart_initnx_rv64im_sim_init+5
55func run_fast_dev(code: *u8, nb: i64, dev_present: i64, steps_out: *i64, us_out: *i64) -> i64
called by 1: main calls 6: sys_mmapfk_predecodemk_virtiosys_now_usfk_runfk_ld
71func main() -> i64
calls 11: g_putssys_mmaprvasm_assemble_strsys_exitrun_sim_devrun_fast_dev+5