rv64im_min_decoder.nx

rv64im_min_decoder.nx -- first concrete use of the NishiHDL DSL. Decodes RV64I + M instructions into a sealed-enum opcode kind + operand-extracted fields (rd, rs1, rs2, immediate). This is the fetch-decode stage of the Tier A FPGA target (see hdl/rv64im_min_target_spec.md for the silicon contract). Status: SEED. 2026-05-26. Decoder logic only; execute / mem / writeback land in follow-on commits. Why decoder first: 1. Smallest standalone module that exercises every NishiHDL primitive (wires, modules, connect, sealed enums). 2. Verifiable against ANY known RV64IM-binary -- correctness can be ground-truthed before any execute logic exists. 3. Decoder shape is identical across single-cycle, 5-stage, and out-of-order pipelines; so this module survives any future pipeline-style change. RV64I instruction format (per riscv-spec): bits 31..25 funct7 bits 24..20 rs2 bits 19..15 rs1 bits 14..12 funct3 bits 11..7 rd bits 6..0 opcode The seven base RV64I opcodes (low 7 bits): 0110011 R-type add/sub/sll/slt/sltu/xor/srl/sra/or/and (also M ext) 0010011 I-type addi/slti/sltiu/xori/ori/andi/slli/srli/srai 0000011 Load lb/lh/lw/ld/lbu/lhu/lwu 0100011 Store sb/sh/sw/sd 1100011 Branch beq/bne/blt/bge/bltu/bgeu 1101111 jal pc-relative jump-and-link 1100111 jalr reg-indirect jump-and-link 0110111 lui load upper immediate 0010111 auipc add upper immediate to pc 1110011 System ecall/ebreak/csrrw/csrrs/csrrc/csrrwi/csrrsi/csrrci 0001111 Fence fence/fence.i