nx_simtcore_gate.nx

nx_simtcore_gate.nx -- GATE: the sovereign SIMT GPGPU core executes real SIMT kernels and reproduces the ARCHITECTURAL RELATIONSHIPS published for Vortex (Georgia Tech). This is the measuring stick for nx_simtcore.nx. It closes the nx_sovgpu_census cell "open GPU core on OUR FPGA (Vortex/Nyuzi class)", previously graded GAP. ===== THE ORACLE ===== Vortex, MICRO'54 2021 (arXiv 2110.10857). The paper publishes NO per-benchmark absolute IPC in its text -- the IPC figures are plots, and their y-axes are labelled CPI while the captions say IPC, a contradiction the paper never resolves. So absolute IPC is NOT a usable oracle and we do not pretend it is. What the paper DOES state numerically, in prose, is two config relationships on sgemm -- and all three configs hold TOTAL THREADS CONSTANT at 16, so it is a fair comparison of how you PARTITION the same threads: "Moving from a 4W-4T configuration to a 2W-8T configuration, maximizing threads, introduces a 69% area cost increase in LUT and registers, as well as a speedup of 20% for sgemm." "changing the configuration to 8W-2T, maximizing wavefronts, generates cheaper hardware, about a 27% area reduction. This comes with a reduction in performance in terms of IPC, 36% for sgemm in the extreme case." sgemm is classified COMPUTE-BOUNDED by the same paper. So the falsifiable predictions our core must reproduce on a compute-bound kernel at equal total threads are: P1 2W-8T is FASTER than 4W-4T P2 8W-2T is SLOWER than 4W-4T HONEST SCOPE: we test DIRECTION, not magnitude. Our model has no FPU, no DRAM controller and no FPGA routing, so its idealised speedups are LARGER than Vortex's achieved ones (Vortex got +20%/-36% where a pure issue-width model predicts +100%/-50%). Claiming magnitude agreement would be dishonest; claiming direction agreement is exactly what the evidence supports. P3 is the counterpart the same paper implies and that every GPU exists for: on a MEMORY-BOUND kernel the ordering INVERTS, because more warps hide more latency. A core that reproduces P1/P2 but not P3 has modelled issue width and forgotten latency hiding. ===== TEETH ===== T1 CORRECTNESS -- 16 threads compute a per-thread result matching an independent