nx_simtcore.nx

nx_simtcore.nx -- the SOVEREIGN SIMT GPGPU EXECUTION CORE. This is the missing organ named by our OWN ruler: nx_sovgpu_census grades the cell "open GPU core on OUR FPGA (Vortex/Nyuzi class)" as GAP. This file closes it. It is a SIMT (single-instruction multiple-thread) execution core built from the first bit in NishiLang on top of the sovereign RV64IM decoder + ALU already in nishi-silicon/hdl. WHAT SIMT ADDS OVER THE SCALAR CORE (rv64im_min_sim): scalar core : 1 PC, 1 register file, 1 instruction -> 1 result SIMT core : NW warps, each with 1 PC and a THREAD MASK; each warp owns NT threads; each thread owns its own 32-entry register file. One fetched instruction executes in lockstep across every ACTIVE thread of the selected warp. A masked-off thread commits NOTHING -- no register write, no memory write. That single rule is what makes control-flow divergence expressible on a machine with one PC. ===== BENCHMARK ORACLE (external, measured, never copied) ===== Vortex (Georgia Tech, MICRO'54 2021, arXiv 2110.10857) is the reference open-source RISC-V GPGPU. We use its PUBLISHED ARCHITECTURE AND MEASUREMENTS as a measuring stick. We copy no Vortex source, RTL, or asset. Verified facts driving this design: - Vortex extends RISC-V with SIX instructions: wspawn, tmc, split, join, bar, tex. "by adding only six new instructions to the standard RISC-V ISA" (MICRO'21 sec 1). - Divergence uses an IPDOM (immediate post-dominator) stack, TWO pushes per split. - Thread mask: "If the bit in the thread mask for a specific thread is zero, no modifications would be made to that thread's register file and no changes to the cache would be made based on that thread." (arXiv 2002.12151). - Scheduler picks ONE wavefront per cycle from a visible mask; stalled/barrier masks remove warps from contention (MICRO'21 sec 4.1.1). - Cache banks are kept equal to the threads-per-warp count (CARRV 2019). - Baseline config 4W-4T; configs evaluated 4W-4T, 2W-8T, 8W-2T, 4W-8T, 8W-4T. ===== SOVEREIGN ENCODING, NOT VORTEX'S ===== RISC-V reserves four opcodes for user extensions: 0x0B, 0x2B, 0x5B, 0x7B. Vortex documents 0x5B for its `tex`. We take custom-0 = 0x0B so there is ZERO encoding collision with Vortex: the CAPABILITY set is benchmarked, the BITS are our own. NEVER-BRICK (cardinal 26): this core is a pure behavioural model over caller-owned memory. It writes no firmware, no device, no persistent hardware state. It is deterministic and bounded by construction -- every run is replayable bit-for-bit. Status: SEED. 2026-07-31. license_tier: ORIGINAL expect_exit: 0