nishi_hdl_primitives.nx

nishi_hdl_primitives.nx -- Nishi HDL DSL primitive types. THE seed file for the NishiLang-hosted hardware description DSL. Defines just the type primitives -- Module, Wire, Reg, Bus, Clock -- so the first concrete user (rv64im_min_decoder.nx) has a vocabulary to express logic in. Status: SEED. 2026-05-26. Types only; behavior (simulation, netlist emit, synth) lands in follow-on commits per hdl/README.md deliverables checklist. Cardinal "bits up, additive intelligence": these types are the substrate the DSL builds on. Future commits add lex/parse/sim/ netlist layers ABOVE them, NOT replacements OF them. Why NishiLang-hosted vs free-standing DSL syntax: feedback-no-nxc2-c-extension-only-nishilang-forward -- the whole stack is NishiLang. Verilog/SystemVerilog/Chisel/Migen are external; substrate's HDL is just NishiLang types + functions. The "DSL" is a coding convention + a constructor library. Surface comparison: Verilog 2005: wire [7:0] data; Chisel (Scala): val data = Wire(UInt(8.W)) NishiHDL: let data: NxHdlWire = nx_hdl_wire_make(width=8) The width-typed value flows through Module-graph constructors; nishi-synth (future) reads the graph and emits a gate netlist.