rv64im_min_clint.nx

rv64im_min_clint.nx -- Core-Local Interruptor (CLINT) MMIO device. Drives the kernel's preemptive timer. Two memory-mapped registers: MTIME (0x0200BFF8, 64-bit RO from CPU side) Monotonic counter; advances 1 per fabric-clock tick. Kernel reads it on every preempt-tick handler to measure latency. MTIMECMP[0] (0x02004000, 64-bit RW) Per-hart compare register. When MTIME >= MTIMECMP[0], the CLINT asserts MTIP on the hart; the CPU takes a machine-timer interrupt (mcause = (1 << 63) | 7) if mstatus.MIE and mie.MTIE are both set. Kernel rearms by writing MTIMECMP[0] = MTIME + TICK_CYCLES. Tier A FPGA: single-hart only, so MTIMECMP[N] for N>0 is absent. The full RISC-V CLINT spec also defines MSIP (software interrupt) at 0x02000000, but the kernel never uses it -- omitted here per the spec's "must implement enough that kernel boots" cardinal. Memory map (matches QEMU virt machine; kernel hardcodes these): 0x02000000 MSIP[0] -- NOT IMPLEMENTED in Tier A (4 bytes) 0x02004000 MTIMECMP[0] -- 8 bytes 0x02004008..0x0200BFF7 sparse; reads/writes return 0 0x0200BFF8 MTIME -- 8 bytes 0x0200C000 end of region Status: SEED. 2026-05-26. Register storage + access + interrupt generation. Synth target: 2 64-bit flop registers + comparator + memory-region address decoder. Tier A FPGA: trivial.