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nx_nxc_baremetal.nx

buildroot/runtime/_hdl_build/nx_nxc_baremetal.nx

7545 B95 linesdepth 5pulls 17 transitivereach 0 importersview sourcekind tooltopic nxc
docsdependenciesstructsconstsfunctions

about

nx_nxc_baremetal.nx -- THE FULL PRODUCT LOOP: NishiLang SOURCE -> self-hosted nxc -> RV64 ELF -> QEMU-validated emulator. Reads a NishiLang program compiled to a RISC-V Linux ELF by the SOVEREIGN self-hosted nxc (source -> lex -> parse -> IR -> opt -> regalloc -> riscv -> ELF), extracts its .text, and bridges the Linux-ELF -> bare-metal gap: prepend an sp shim (Linux gives argc/argv on the stack; bare-metal doesn't), patch the codegen's `li a7,93; ecall` exit to a `jal` to a UART-emit(a0) + SiFive-finisher epilogue (assembled by the sovereign nx_rv64_asm). Runs the result on the QEMU-validated golden sim (rv64im_min_sim) + writes a flat bin for qemu-system-riscv64 (the liar-killer). sum10.nx returns 55 = 0x37. So the WHOLE sovereign source->RISC-V toolchain is validated against QEMU. expect_exit: 0

dependencies 12 imports · 0 importers

nx_syscalls.nx nishi_hdl_primitives.nx rv64im_min_decoder.nx rv64im_min_alu.nx rv64im_min_regfile.nx rv64im_min_csr.nx rv64im_min_clint.nx rv64im_min_uart.nx rv64im_min_virtio.nx rv64im_min_mmu.nx nx_nxc_baremetal.nx

diagram shows first 10 each side; +2 more imports, +0 more importers in the complete lists below.

imports: nx_syscalls.nxnishi_hdl_primitives.nxrv64im_min_decoder.nxrv64im_min_alu.nxrv64im_min_regfile.nxrv64im_min_csr.nxrv64im_min_clint.nxrv64im_min_uart.nxrv64im_min_virtio.nxrv64im_min_mmu.nxrv64im_min_sim.nxnx_rv64_asm.nx

imported by: nobody (leaf or entry point)

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

main g_puts sys_write sys_mmap sys_read_file sys_openat_rd sys_lseek sys_mmap ↻ sys_read sys_close sys_exit g_pn sys_mmap ↻ sys_write ↻ get32 ck g_puts ↻ put32 enc_jal_x0 rvasm_assemble_str rvasm_assemble sys_mmap ↻ ra_isws ra_encode sys_mmap ↻ ra_afterword ra_isws ↻ ra_word_is ra_isws ↻ ra_reg ra_skipsep ra_isws ↻ ra_num ra_isdig ra_imm ra_skipsep ↻ ra_ishex ra_isdig ↻ ra_hexval ra_isdig ↻

structs

none

consts

20const DMEM_MAGIC_4096: i64 = 4096
21const DMEM_MAGIC_100000000: i64 = 100000000
28const DMEM_BASE: i64 = 0x80000000
29const DMEM_SIZE: i64 = 262144
30const ELF_HDR: i64 = 120 // nxc ELF: 64B ELF header + 56B program header; code (entry) starts here

functions

23func g_puts(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 }
called by 2: ckmain calls 1: sys_write
24func g_pn(v: i64) -> i64 { let b: *u8=sys_mmap(28); var x: i64=v; if x==0{b[0]=48;sys_write(1,b,1);return 0} var d: i64=0; var y: i64=x; while y>0{d=d+1;y=y/10} var i: i64=d-1; y=x; while i>=0{b[i]=(48+(y%10)) as u8;y=y/10;i=i-1} sys_write(1,b,d); return 0 }
called by 1: main calls 2: sys_mmapsys_write
25func g_hx(v: i64) -> i64 { let b: *u8=sys_mmap(4); let n0: i64=(v>>4)&15; let n1: i64=v&15; if n0<10 { b[0]=(48+n0) as u8 } else { b[0]=(87+n0) as u8 } if n1<10 { b[1]=(48+n1) as u8 } else { b[1]=(87+n1) as u8 } b[2]=32 as u8; sys_write(1,b,3); return 0 }
called by 1: main calls 2: sys_mmapsys_write
26func ck(name: *u8, c: i64) -> i64 { if c==1 { g_puts(" PASS " as *u8) } else { g_puts(" FAIL " as *u8) } g_puts(name); g_puts("\n" as *u8); return c }
called by 1: main calls 1: g_puts
32func put32(m: *u8, o: i64, w: i64) -> i64 { m[o]=(w&0xff) as u8; m[o+1]=((w>>8)&0xff) as u8; m[o+2]=((w>>16)&0xff) as u8; m[o+3]=((w>>24)&0xff) as u8; return 0 }
called by 1: main
33func get32(m: *u8, o: i64) -> i64 { return (m[o] as i64)|((m[o+1] as i64)<<8)|((m[o+2] as i64)<<16)|((m[o+3] as i64)<<24) }
called by 1: main
35func enc_jal_x0(imm: i64) -> i64
called by 1: main
40func main() -> i64
calls 22: g_putssys_mmapsys_read_filesys_exitg_pnget32+16